changeset a113f27b68bd in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a113f27b68bd
description:
        cpu: Introduce sanity checks when switching between CPUs

        This patch introduces the following sanity checks when switching
        between CPUs:

         * Check that the set of new and old CPUs do not overlap. Having an
           overlap between the set of new CPUs and the set of old CPUs is
           currently not supported. Doing such a switch used to result in the
           following assertion error:
             BaseCPU::takeOverFrom(BaseCPU*): \
               Assertion `!new_itb_port->isConnected()' failed.

         * Check that all new CPUs are in the switched out state.

         * Check that all old CPUs are in the switched in state.

diffstat:

 src/cpu/BaseCPU.py        |   1 +
 src/cpu/base.cc           |   6 ++++++
 src/cpu/base.hh           |  12 +++++++++++-
 src/python/m5/simulate.py |  10 ++++++++++
 4 files changed, 28 insertions(+), 1 deletions(-)

diffs (102 lines):

diff -r 7c787b8030c6 -r a113f27b68bd src/cpu/BaseCPU.py
--- a/src/cpu/BaseCPU.py        Mon Jan 07 13:05:44 2013 -0500
+++ b/src/cpu/BaseCPU.py        Mon Jan 07 13:05:44 2013 -0500
@@ -95,6 +95,7 @@
         code('''
     void switchOut();
     void takeOverFrom(BaseCPU *cpu);
+    bool switchedOut();
 ''')
 
     def takeOverFrom(self, old_cpu):
diff -r 7c787b8030c6 -r a113f27b68bd src/cpu/base.cc
--- a/src/cpu/base.cc   Mon Jan 07 13:05:44 2013 -0500
+++ b/src/cpu/base.cc   Mon Jan 07 13:05:44 2013 -0500
@@ -119,6 +119,7 @@
       _instMasterId(p->system->getMasterId(name() + ".inst")),
       _dataMasterId(p->system->getMasterId(name() + ".data")),
       _taskId(ContextSwitchTaskId::Unknown), _pid(Request::invldPid),
+      _switchedOut(p->defer_registration),
       interrupts(p->interrupts), profileEvent(NULL),
       numThreads(p->numThreads), system(p->system)
 {
@@ -356,6 +357,8 @@
 void
 BaseCPU::switchOut()
 {
+    assert(!_switchedOut);
+    _switchedOut = true;
     if (profileEvent && profileEvent->scheduled())
         deschedule(profileEvent);
 }
@@ -365,8 +368,11 @@
 {
     assert(threadContexts.size() == oldCPU->threadContexts.size());
     assert(_cpuId == oldCPU->cpuId());
+    assert(_switchedOut);
+    assert(oldCPU != this);
     _pid = oldCPU->getPid();
     _taskId = oldCPU->taskId();
+    _switchedOut = false;
 
     ThreadID size = threadContexts.size();
     for (ThreadID i = 0; i < size; ++i) {
diff -r 7c787b8030c6 -r a113f27b68bd src/cpu/base.hh
--- a/src/cpu/base.hh   Mon Jan 07 13:05:44 2013 -0500
+++ b/src/cpu/base.hh   Mon Jan 07 13:05:44 2013 -0500
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011 ARM Limited
+ * Copyright (c) 2011-2012 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -114,6 +114,9 @@
      * used to generate a taskId */
     uint32_t _pid;
 
+    /** Is the CPU switched out or active? */
+    bool _switchedOut;
+
     /**
      * Define a base class for the CPU ports (instruction and data)
      * that is refined in the subclasses. This class handles the
@@ -321,6 +324,13 @@
     virtual void takeOverFrom(BaseCPU *cpu);
 
     /**
+     * Determine if the CPU is switched out.
+     *
+     * @return True if the CPU is switched out, false otherwise.
+     */
+    bool switchedOut() const { return _switchedOut; }
+
+    /**
      *  Number of threads we're actually simulating (<= SMT_MAX_THREADS).
      * This is a constant for the duration of the simulation.
      */
diff -r 7c787b8030c6 -r a113f27b68bd src/python/m5/simulate.py
--- a/src/python/m5/simulate.py Mon Jan 07 13:05:44 2013 -0500
+++ b/src/python/m5/simulate.py Mon Jan 07 13:05:44 2013 -0500
@@ -228,11 +228,21 @@
         if not isinstance(item, tuple) or len(item) != 2:
             raise RuntimeError, "List must have tuples of (oldCPU,newCPU)"
 
+    old_cpu_set = set([old_cpu for old_cpu, new_cpu in cpuList])
     for old_cpu, new_cpu in cpuList:
         if not isinstance(old_cpu, objects.BaseCPU):
             raise TypeError, "%s is not of type BaseCPU" % old_cpu
         if not isinstance(new_cpu, objects.BaseCPU):
             raise TypeError, "%s is not of type BaseCPU" % new_cpu
+        if new_cpu in old_cpu_set:
+            raise RuntimeError, \
+                "New CPU (%s) is in the list of old CPUs." % (old_cpu,)
+        if not new_cpu.switchedOut():
+            raise RuntimeError, \
+                "New CPU (%s) is already active." % (new_cpu,)
+        if old_cpu.switchedOut():
+            raise RuntimeError, \
+                "Old CPU (%s) is inactive." % (new_cpu,)
 
     # Now all of the CPUs are ready to be switched out
     for old_cpu, new_cpu in cpuList:
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