changeset f902aa5773a8 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f902aa5773a8
description:
cpu: Remove unused params.hh header file in inorder CPU
diffstat:
src/cpu/inorder/first_stage.hh | 1 -
src/cpu/inorder/params.hh | 122 -------------------------
src/cpu/inorder/pipeline_traits.5stage.hh | 1 -
src/cpu/inorder/pipeline_traits.9stage.hh | 1 -
src/cpu/inorder/pipeline_traits.9stage.smt2.hh | 1 -
src/cpu/inorder/resource_pool.hh | 1 -
src/cpu/inorder/resources/agen_unit.hh | 1 -
7 files changed, 0 insertions(+), 128 deletions(-)
diffs (192 lines):
diff -r 8bb372a49e1b -r f902aa5773a8 src/cpu/inorder/first_stage.hh
--- a/src/cpu/inorder/first_stage.hh Mon Jan 07 13:05:44 2013 -0500
+++ b/src/cpu/inorder/first_stage.hh Mon Jan 07 13:05:45 2013 -0500
@@ -38,7 +38,6 @@
#include "base/statistics.hh"
#include "cpu/inorder/comm.hh"
#include "cpu/inorder/inorder_dyn_inst.hh"
-#include "cpu/inorder/params.hh"
#include "cpu/inorder/pipeline_stage.hh"
#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/timebuf.hh"
diff -r 8bb372a49e1b -r f902aa5773a8 src/cpu/inorder/params.hh
--- a/src/cpu/inorder/params.hh Mon Jan 07 13:05:44 2013 -0500
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,122 +0,0 @@
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Korey Sewell
- */
-
-#ifndef __CPU_INORDER_PARAMS_HH__
-#define __CPU_INORDER_PARAMS_HH__
-
-#include "cpu/base.hh"
-
-//Forward declarations
-class FunctionalMemory;
-class Process;
-class MemObject;
-class MemInterface;
-
-/**
- * This file defines the parameters that will be used for the InOrderCPU.
- * This must be defined externally so that the Impl can have a params class
- * defined that it can pass to all of the individual stages.
- */
-
-class InOrderParams : public BaseCPU::Params
-{
- public:
-
- // Workloads
- std::vector<Process *> workload;
- Process *process;
-
- //
- // Memory System/Caches
- //
- unsigned cachePorts;
- std::string fetchMemPort;
- std::string dataMemPort;
-
- //
- // Branch predictor (BP & BTB)
- //
- std::string predType;
- unsigned localPredictorSize;
- unsigned localCtrBits;
- unsigned localHistoryTableSize;
- unsigned localHistoryBits;
- unsigned globalPredictorSize;
- unsigned globalCtrBits;
- unsigned globalHistoryBits;
- unsigned choicePredictorSize;
- unsigned choiceCtrBits;
- unsigned BTBEntries;
- unsigned BTBTagSize;
- unsigned RASSize;
-
- // Pipeline Parameters
- unsigned stageWidth;
-
- // InOrderCPU Simulation Parameters
- unsigned instShiftAmt;
- unsigned activity;
- unsigned deferRegistration;
-
- //
- // Memory Parameters
- //
- unsigned memBlockSize;
-
- //
- // Multiply Divide Unit
- //
- // @NOTE: If >1 MDU is needed and each MDU is to use varying parametesr,
- // then MDU must be defined as its own SimObject so that an arbitrary # can
- // be defined with different parameters
- /** Latency & Repeat Rate for Multiply Insts */
- Cycles multLatency;
- Cycles multRepeatRate;
-
- /** Latency & Repeat Rate for 8-bit Divide Insts */
- Cycles div8Latency;
- Cycles div8RepeatRate;
-
- /** Latency & Repeat Rate for 16-bit Divide Insts */
- Cycles div16Latency;
- Cycles div16RepeatRate;
-
- /** Latency & Repeat Rate for 24-bit Divide Insts */
- Cycles div24Latency;
- Cycles div24RepeatRate;
-
- /** Latency & Repeat Rate for 32-bit Divide Insts */
- Cycles div32Latency;
- Cycles div32RepeatRate;
-
-
-};
-
-#endif // _CPU_INORDER_PARAMS_HH__
diff -r 8bb372a49e1b -r f902aa5773a8 src/cpu/inorder/pipeline_traits.5stage.hh
--- a/src/cpu/inorder/pipeline_traits.5stage.hh Mon Jan 07 13:05:44 2013 -0500
+++ b/src/cpu/inorder/pipeline_traits.5stage.hh Mon Jan 07 13:05:45 2013 -0500
@@ -37,7 +37,6 @@
#include <vector>
#include "arch/isa_traits.hh"
-#include "cpu/inorder/params.hh"
class InOrderDynInst;
diff -r 8bb372a49e1b -r f902aa5773a8 src/cpu/inorder/pipeline_traits.9stage.hh
--- a/src/cpu/inorder/pipeline_traits.9stage.hh Mon Jan 07 13:05:44 2013 -0500
+++ b/src/cpu/inorder/pipeline_traits.9stage.hh Mon Jan 07 13:05:45 2013 -0500
@@ -38,7 +38,6 @@
#include <vector>
#include "arch/isa_traits.hh"
-#include "cpu/inorder/params.hh"
class InOrderDynInst;
diff -r 8bb372a49e1b -r f902aa5773a8
src/cpu/inorder/pipeline_traits.9stage.smt2.hh
--- a/src/cpu/inorder/pipeline_traits.9stage.smt2.hh Mon Jan 07 13:05:44
2013 -0500
+++ b/src/cpu/inorder/pipeline_traits.9stage.smt2.hh Mon Jan 07 13:05:45
2013 -0500
@@ -38,7 +38,6 @@
#include <vector>
#include "arch/isa_traits.hh"
-#include "cpu/inorder/params.hh"
class InOrderDynInst;
diff -r 8bb372a49e1b -r f902aa5773a8 src/cpu/inorder/resource_pool.hh
--- a/src/cpu/inorder/resource_pool.hh Mon Jan 07 13:05:44 2013 -0500
+++ b/src/cpu/inorder/resource_pool.hh Mon Jan 07 13:05:45 2013 -0500
@@ -49,7 +49,6 @@
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/inorder_dyn_inst.hh"
-#include "cpu/inorder/params.hh"
#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inorder/resource.hh"
#include "cpu/inst_seq.hh"
diff -r 8bb372a49e1b -r f902aa5773a8 src/cpu/inorder/resources/agen_unit.hh
--- a/src/cpu/inorder/resources/agen_unit.hh Mon Jan 07 13:05:44 2013 -0500
+++ b/src/cpu/inorder/resources/agen_unit.hh Mon Jan 07 13:05:45 2013 -0500
@@ -38,7 +38,6 @@
#include "cpu/inorder/cpu.hh"
#include "cpu/inorder/inorder_dyn_inst.hh"
-#include "cpu/inorder/params.hh"
#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inorder/resource.hh"
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