changeset 68f7e0bcf4aa in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=68f7e0bcf4aa
description:
x86: implement fabs, fchs instructions
diffstat:
src/arch/x86/isa/decoder/x87.isa | 4 ++--
src/arch/x86/isa/insts/x87/arithmetic/change_sign.py | 10 ++++++++--
src/arch/x86/isa/microops/fpop.isa | 8 ++++++++
src/arch/x86/isa/operands.isa | 4 ++++
src/arch/x86/regs/misc.hh | 19 +++++++++++++++++++
5 files changed, 41 insertions(+), 4 deletions(-)
diffs (92 lines):
diff -r d2eeba87c4a8 -r 68f7e0bcf4aa src/arch/x86/isa/decoder/x87.isa
--- a/src/arch/x86/isa/decoder/x87.isa Mon Jan 14 10:20:16 2013 -0600
+++ b/src/arch/x86/isa/decoder/x87.isa Tue Jan 15 07:43:19 2013 -0600
@@ -68,8 +68,8 @@
}
0x4: decode MODRM_MOD {
0x3: decode MODRM_RM {
- 0x0: fchs();
- 0x1: fabs();
+ 0x0: Inst::FCHS();
+ 0x1: Inst::FABS();
0x4: ftst();
0x5: fxam();
default: Inst::UD2();
diff -r d2eeba87c4a8 -r 68f7e0bcf4aa
src/arch/x86/isa/insts/x87/arithmetic/change_sign.py
--- a/src/arch/x86/isa/insts/x87/arithmetic/change_sign.py Mon Jan 14
10:20:16 2013 -0600
+++ b/src/arch/x86/isa/insts/x87/arithmetic/change_sign.py Tue Jan 15
07:43:19 2013 -0600
@@ -36,6 +36,12 @@
# Authors: Gabe Black
microcode = '''
-# FABS
-# FCHS
+
+def macroop FABS {
+ absfp st(0), st(0)
+};
+
+def macroop FCHS {
+ chsfp st(0), st(0)
+};
'''
diff -r d2eeba87c4a8 -r 68f7e0bcf4aa src/arch/x86/isa/microops/fpop.isa
--- a/src/arch/x86/isa/microops/fpop.isa Mon Jan 14 10:20:16 2013 -0600
+++ b/src/arch/x86/isa/microops/fpop.isa Tue Jan 15 07:43:19 2013 -0600
@@ -331,4 +331,12 @@
else if(FpSrcReg1 == FpSrcReg2)
ccFlagBits = ccFlagBits | ZFBit;
'''
+
+ class absfp(FpUnaryOp):
+ code = 'FpDestReg = fabs(FpSrcReg1);'
+ flag_code = 'FSW &= (~CC1Bit);'
+
+ class chsfp(FpUnaryOp):
+ code = 'FpDestReg = (-1) * (FpSrcReg1);'
+ flag_code = 'FSW &= (~CC1Bit);'
}};
diff -r d2eeba87c4a8 -r 68f7e0bcf4aa src/arch/x86/isa/operands.isa
--- a/src/arch/x86/isa/operands.isa Mon Jan 14 10:20:16 2013 -0600
+++ b/src/arch/x86/isa/operands.isa Tue Jan 15 07:43:19 2013 -0600
@@ -158,7 +158,11 @@
# These register should needs to be more protected so that later
# instructions don't map their indexes with an old value.
'nccFlagBits': controlReg('MISCREG_RFLAGS', 65),
+
+ # Registers related to the state of x87 floating point unit.
'TOP': controlReg('MISCREG_X87_TOP', 66, ctype='ub'),
+ 'FSW': controlReg('MISCREG_FSW', 67, ctype='uw'),
+
# The segment base as used by memory instructions.
'SegBase': controlReg('MISCREG_SEG_EFF_BASE(segment)', 70),
diff -r d2eeba87c4a8 -r 68f7e0bcf4aa src/arch/x86/regs/misc.hh
--- a/src/arch/x86/regs/misc.hh Mon Jan 14 10:20:16 2013 -0600
+++ b/src/arch/x86/regs/misc.hh Tue Jan 15 07:43:19 2013 -0600
@@ -79,6 +79,25 @@
IDBit = 1 << 21
};
+ enum X87StatusBit {
+ // Exception Flags
+ IEBit = 1 << 0,
+ DEBit = 1 << 1,
+ ZEBit = 1 << 2,
+ OEBit = 1 << 3,
+ UEBit = 1 << 4,
+ PEBit = 1 << 5,
+
+ // !Exception Flags
+ StackFaultBit = 1 << 6,
+ ErrSummaryBit = 1 << 7,
+ CC0Bit = 1 << 8,
+ CC1Bit = 1 << 9,
+ CC2Bit = 1 << 10,
+ CC3Bit = 1 << 14,
+ BusyBit = 1 << 15,
+ };
+
enum MiscRegIndex
{
// Control registers
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