Any comments on the new patch? Thanks, Amin
On Sat, Jan 19, 2013 at 1:49 AM, Amin Farmahini <[email protected]> wrote: > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1422/ > Review request for Default. > By Amin Farmahini. > > *Updated Jan. 18, 2013, 11:49 p.m.* > Description (updated) > > I made some changes to O3 to model the bandwidth between O3 and L1. By > bandwidth I mean the number of requests and responses sent or received each > cycle (not the amount of data transferred). I limit both the number of > requests sent by O3 and the number of responses received by O3. > > For REQUESTS: > I have a separate read requests (loads) counter and a separate write requests > (stores) counter and a separate shared requests (read/write) counter. > LOADS: O3 limits the number of read requests sent each cycle to the number of > defined cache read ports. > STORES: Similarly, O3 limits the number of write requests sent each cycle to > the number of defined cache write ports. > Also, shared ports can be used for read/write requests. > Note that no matter how many ports are defined, we have only a single actual > cache port used for all read and write requests. So just like the current > gem5 code, only one dcachePort is defined in the code. However, I limit the > number of requests to the number of cache ports defined in parameters. > > For RESPONSES: > If there are not enough cache ports, response packets are buffered in the > port (cache side) and are sent to the processor next cycle. > > I don't believe what I implemented is the best way to model cache ports here, > so your feedback would be appreciated. > > Testing > > a few small benches done only in SE and classic > > Diffs > > - src/cpu/base_dyn_inst.hh (UNKNOWN) > - src/cpu/o3/O3CPU.py (UNKNOWN) > - src/cpu/o3/iew_impl.hh (UNKNOWN) > - src/cpu/o3/inst_queue.hh (UNKNOWN) > - src/cpu/o3/inst_queue_impl.hh (UNKNOWN) > - src/cpu/o3/lsq.hh (UNKNOWN) > - src/cpu/o3/lsq_impl.hh (UNKNOWN) > - src/cpu/o3/lsq_unit.hh (UNKNOWN) > - src/cpu/o3/lsq_unit_impl.hh (UNKNOWN) > - src/mem/cache/BaseCache.py (UNKNOWN) > - src/mem/cache/base.hh (UNKNOWN) > - src/mem/cache/base.cc (UNKNOWN) > - src/mem/cache/cache.hh (UNKNOWN) > - src/mem/cache/cache_impl.hh (UNKNOWN) > - src/mem/packet_queue.hh (UNKNOWN) > - src/mem/packet_queue.cc (UNKNOWN) > - src/mem/port.hh (UNKNOWN) > - src/mem/port.cc (UNKNOWN) > - src/sim/clocked_object.hh (UNKNOWN) > > View Diff <http://reviews.gem5.org/r/1422/diff/> > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
