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Ship it! Ship It! - Steve Reinhardt On Feb. 14, 2013, 2:57 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1715/ > ----------------------------------------------------------- > > (Updated Feb. 14, 2013, 2:57 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9521:523d0e0d4f36 > --------------------------- > mem: Enforce strict use of busFirst- and busLastWordTime > > This patch adds a check to ensure that the delay incurred by > the bus is not simply disregarded, but accounted for by someone. At > this point, all the modules do is to zero it out, and no additional > time is spent. This highlights where the bus timing is simply dropped > instead of being paid for. > > As a follow up, the locations identified in this patch should add this > additional time to the packets in one way or another. For now it > simply acts as a sanity check and highlights where the delay is simply > ignored. > > Since no time is added, all regressions remain the same. > > > Diffs > ----- > > src/dev/io_device.cc 921d858c5bc7 > src/dev/pcidev.cc 921d858c5bc7 > src/dev/x86/intdev.hh 921d858c5bc7 > src/mem/bridge.cc 921d858c5bc7 > src/mem/bus.cc 921d858c5bc7 > src/mem/cache/cache_impl.hh 921d858c5bc7 > src/mem/coherent_bus.cc 921d858c5bc7 > src/mem/noncoherent_bus.cc 921d858c5bc7 > src/mem/simple_dram.cc 921d858c5bc7 > src/mem/simple_mem.cc 921d858c5bc7 > > Diff: http://reviews.gem5.org/r/1715/diff/ > > > Testing > ------- > > All regressions passing (excluding t1000 and eio) > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
