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(Updated Feb. 18, 2013, 11:04 a.m.) Review request for Default. Description (updated) ------- Changeset 9543:d67d38fdc178 --------------------------- O3 CPU: allow the fetch buffer to be smaller than a cache line the current implementation of the fetch buffer in the o3 cpu is only allowed to be the size of a cache line. some architectures, e.g., ARM, have fetch buffers smaller than a cache line, see slide 22 at: http://www.arm.com/files/pdf/at-exploring_the_design_of_the_cortex-a15.pdf this patch allows the fetch buffer to be set to values smaller than a cache line. Diffs (updated) ----- configs/common/O3_ARM_v7a.py 0ac00d9a8aaf8be3749dbe03b3992e8d24ef9b07 src/cpu/o3/O3CPU.py 0ac00d9a8aaf8be3749dbe03b3992e8d24ef9b07 src/cpu/o3/fetch.hh 0ac00d9a8aaf8be3749dbe03b3992e8d24ef9b07 src/cpu/o3/fetch_impl.hh 0ac00d9a8aaf8be3749dbe03b3992e8d24ef9b07 Diff: http://reviews.gem5.org/r/1726/diff/ Testing ------- ran several of the shorter SPEC CPU2006 benchmarks with test input. icache.overall_accesses::total stat was validated against real cortex A15 hardware, the value is much closer now. Thanks, Anthony Gutierrez _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
