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Review request for Default. Description ------- Changeset 9710:c8358e51438e --------------------------- mem: Add bytes per activate DRAM controller stat This patch adds a histogram to track how many bytes are accessed in an open row before it is closed. This metric is useful in characterising a workload and the efficiency of the DRAM scheduler. For example, a DDR3-1600 device requires 44 cycles (tRC) before it can activate another row in the same bank. For a x32 interface (8 bytes per cycle) that means 8 x 44 = 352 bytes must be transferred to hide the preparation time. Diffs ----- src/mem/simple_dram.hh eb075b2b925a src/mem/simple_dram.cc eb075b2b925a Diff: http://reviews.gem5.org/r/1868/diff/ Testing ------- All regressions pass with stats added Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
