changeset 67d9da312ef0 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=67d9da312ef0
description:
ruby: add stats to .sm files, remove cache profiler
This patch changes the way cache statistics are collected in ruby.
As of now, there is separate entity called CacheProfiler which holds
statistical variables for caches. The CacheMemory class defines
different
functions for accessing the CacheProfiler. These functions are then
invoked
in the .sm files. I find this approach opaque and prone to error.
Secondly,
we probably should not be paying the cost of a function call for
recording
statistics.
Instead, this patch allows for accessing statistical variables in the
.sm files. The collection would become transparent. Secondly, it would
happen
in place, so no function calls. The patch also removes the
CacheProfiler class.
diffstat:
src/mem/protocol/MESI_CMP_directory-L1cache.sm | 46 +++---
src/mem/protocol/MESI_CMP_directory-L2cache.sm | 28 +--
src/mem/protocol/MI_example-cache.sm | 12 +-
src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 58 ++++---
src/mem/protocol/MOESI_CMP_directory-L2cache.sm | 22 ++-
src/mem/protocol/MOESI_CMP_token-L1cache.sm | 98 ++++++++++----
src/mem/protocol/MOESI_CMP_token-L2cache.sm | 30 +--
src/mem/protocol/MOESI_hammer-cache.sm | 155 ++++++++++++++++-----
src/mem/protocol/RubySlicc_Exports.sm | 33 ----
src/mem/protocol/RubySlicc_Types.sm | 10 +-
src/mem/ruby/profiler/CacheProfiler.cc | 165 -----------------------
src/mem/ruby/profiler/CacheProfiler.hh | 88 ------------
src/mem/ruby/profiler/Profiler.hh | 1 -
src/mem/ruby/profiler/SConscript | 1 -
src/mem/ruby/system/CacheMemory.cc | 167 +++++++++++++----------
src/mem/ruby/system/CacheMemory.hh | 31 ++--
src/mem/slicc/ast/InfixOperatorExprAST.py | 91 -------------
src/mem/slicc/ast/OperatorExprAST.py | 112 ++++++++++++++++
src/mem/slicc/ast/__init__.py | 2 +-
src/mem/slicc/parser.py | 8 +-
src/mem/slicc/symbols/StateMachine.py | 6 +-
21 files changed, 521 insertions(+), 643 deletions(-)
diffs (truncated from 2113 to 300 lines):
diff -r b1be1df904c9 -r 67d9da312ef0
src/mem/protocol/MESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm Tue May 14 18:39:47
2013 -0400
+++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm Tue May 21 11:31:31
2013 -0500
@@ -874,16 +874,20 @@
wakeUpBuffers(address);
}
- action(uu_profileInstMiss, "\ui", desc="Profile the demand miss") {
- peek(mandatoryQueue_in, RubyRequest) {
- L1IcacheMemory.profileMiss(in_msg);
- }
+ action(uu_profileInstMiss, "\uim", desc="Profile the demand miss") {
+ ++L1IcacheMemory.demand_misses;
}
- action(uu_profileDataMiss, "\ud", desc="Profile the demand miss") {
- peek(mandatoryQueue_in, RubyRequest) {
- L1DcacheMemory.profileMiss(in_msg);
- }
+ action(uu_profileInstHit, "\uih", desc="Profile the demand hit") {
+ ++L1IcacheMemory.demand_hits;
+ }
+
+ action(uu_profileDataMiss, "\udm", desc="Profile the demand miss") {
+ ++L1DcacheMemory.demand_misses;
+ }
+
+ action(uu_profileDataHit, "\udh", desc="Profile the demand hit") {
+ ++L1DcacheMemory.demand_hits;
}
action(po_observeMiss, "\po", desc="Inform the prefetcher about the miss") {
@@ -1024,8 +1028,15 @@
}
// Transitions from Shared
- transition(S, {Load,Ifetch}) {
+ transition({S,E,M}, Load) {
h_load_hit;
+ uu_profileDataHit;
+ k_popMandatoryQueue;
+ }
+
+ transition({S,E,M}, Ifetch) {
+ h_load_hit;
+ uu_profileInstHit;
k_popMandatoryQueue;
}
@@ -1049,13 +1060,9 @@
// Transitions from Exclusive
- transition(E, {Load, Ifetch}) {
- h_load_hit;
- k_popMandatoryQueue;
- }
-
- transition(E, Store, M) {
+ transition({E,M}, Store, M) {
hh_store_hit;
+ uu_profileDataHit;
k_popMandatoryQueue;
}
@@ -1087,15 +1094,6 @@
}
// Transitions from Modified
- transition(M, {Load, Ifetch}) {
- h_load_hit;
- k_popMandatoryQueue;
- }
-
- transition(M, Store) {
- hh_store_hit;
- k_popMandatoryQueue;
- }
transition(M, L1_Replacement, M_I) {
forward_eviction_to_cpu;
diff -r b1be1df904c9 -r 67d9da312ef0
src/mem/protocol/MESI_CMP_directory-L2cache.sm
--- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm Tue May 14 18:39:47
2013 -0400
+++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm Tue May 21 11:31:31
2013 -0500
@@ -720,26 +720,12 @@
}
}
- GenericRequestType convertToGenericType(CoherenceRequestType type) {
- if(type == CoherenceRequestType:GETS) {
- return GenericRequestType:GETS;
- } else if(type == CoherenceRequestType:GETX) {
- return GenericRequestType:GETX;
- } else if(type == CoherenceRequestType:GET_INSTR) {
- return GenericRequestType:GET_INSTR;
- } else if(type == CoherenceRequestType:UPGRADE) {
- return GenericRequestType:UPGRADE;
- } else {
- DPRINTF(RubySlicc, "%s\n", type);
- error("Invalid CoherenceRequestType\n");
- }
+ action(uu_profileMiss, "\um", desc="Profile the demand miss") {
+ ++L2cacheMemory.demand_misses;
}
- action(uu_profileMiss, "\u", desc="Profile the demand miss") {
- peek(L1RequestIntraChipL2Network_in, RequestMsg) {
- L2cacheMemory.profileGenericRequest(convertToGenericType(in_msg.Type),
- in_msg.AccessMode, in_msg.Prefetch);
- }
+ action(uu_profileHit, "\uh", desc="Profile the demand hit") {
+ ++L2cacheMemory.demand_hits;
}
action(ww_profileMissNoDir, "\w", desc="Profile this transition at the L2
because Dir won't see the request") {
@@ -922,6 +908,7 @@
ds_sendSharedDataToRequestor;
nn_addSharer;
set_setMRU;
+ uu_profileHit;
jj_popL1RequestQueue;
}
@@ -931,6 +918,7 @@
// fw_sendFwdInvToSharers;
fwm_sendFwdInvToSharersMinusRequestor;
set_setMRU;
+ uu_profileHit;
jj_popL1RequestQueue;
}
@@ -938,6 +926,7 @@
fwm_sendFwdInvToSharersMinusRequestor;
ts_sendInvAckToUpgrader;
set_setMRU;
+ uu_profileHit;
jj_popL1RequestQueue;
}
@@ -957,6 +946,7 @@
transition(M, L1_GETX, MT_MB) {
d_sendDataToRequestor;
set_setMRU;
+ uu_profileHit;
jj_popL1RequestQueue;
}
@@ -964,12 +954,14 @@
d_sendDataToRequestor;
nn_addSharer;
set_setMRU;
+ uu_profileHit;
jj_popL1RequestQueue;
}
transition(M, L1_GETS, MT_MB) {
dd_sendExclusiveDataToRequestor;
set_setMRU;
+ uu_profileHit;
jj_popL1RequestQueue;
}
diff -r b1be1df904c9 -r 67d9da312ef0 src/mem/protocol/MI_example-cache.sm
--- a/src/mem/protocol/MI_example-cache.sm Tue May 14 18:39:47 2013 -0400
+++ b/src/mem/protocol/MI_example-cache.sm Tue May 21 11:31:31 2013 -0500
@@ -335,10 +335,12 @@
profileMsgDelay(2, forwardRequestNetwork_in.dequeue_getDelayCycles());
}
- action(p_profileMiss, "p", desc="Profile cache miss") {
- peek(mandatoryQueue_in, RubyRequest) {
- cacheMemory.profileMiss(in_msg);
- }
+ action(p_profileMiss, "pi", desc="Profile cache miss") {
+ ++cacheMemory.demand_misses;
+ }
+
+ action(p_profileHit, "ph", desc="Profile cache miss") {
+ ++cacheMemory.demand_hits;
}
action(r_load_hit, "r", desc="Notify sequencer the load completed.") {
@@ -427,11 +429,13 @@
transition(M, Store) {
s_store_hit;
+ p_profileHit;
m_popMandatoryQueue;
}
transition(M, {Load, Ifetch}) {
r_load_hit;
+ p_profileHit;
m_popMandatoryQueue;
}
diff -r b1be1df904c9 -r 67d9da312ef0
src/mem/protocol/MOESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Tue May 14 18:39:47
2013 -0400
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Tue May 21 11:31:31
2013 -0500
@@ -1,4 +1,3 @@
-
/*
* Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
* All rights reserved.
@@ -859,10 +858,20 @@
}
}
- action(uu_profileMiss, "\u", desc="Profile the demand miss") {
- peek(mandatoryQueue_in, RubyRequest) {
- // profile_miss(in_msg);
- }
+ action(uu_profileInstMiss, "\uim", desc="Profile the demand miss") {
+ ++L1Icache.demand_misses;
+ }
+
+ action(uu_profileInstHit, "\uih", desc="Profile the demand hit") {
+ ++L1Icache.demand_hits;
+ }
+
+ action(uu_profileDataMiss, "\udm", desc="Profile the demand miss") {
+ ++L1Dcache.demand_misses;
+ }
+
+ action(uu_profileDataHit, "\udh", desc="Profile the demand hit") {
+ ++L1Dcache.demand_hits;
}
action(z_recycleRequestQueue, "z", desc="Send the head of the mandatory
queue to the back of the queue.") {
@@ -899,7 +908,7 @@
ii_allocateL1DCacheBlock;
i_allocateTBE;
a_issueGETS;
- // uu_profileMiss;
+ uu_profileDataMiss;
k_popMandatoryQueue;
}
@@ -907,7 +916,7 @@
jj_allocateL1ICacheBlock;
i_allocateTBE;
a_issueGETS;
- // uu_profileMiss;
+ uu_profileInstMiss;
k_popMandatoryQueue;
}
@@ -915,7 +924,7 @@
ii_allocateL1DCacheBlock;
i_allocateTBE;
b_issueGETX;
- // uu_profileMiss;
+ uu_profileDataMiss;
k_popMandatoryQueue;
}
@@ -928,16 +937,23 @@
l_popForwardQueue;
}
- // Transitions from Shared
- transition({S, SM}, {Load, Ifetch}) {
+ transition({S, SM, O, OM, MM, MM_W, M, M_W}, Load) {
h_load_hit;
+ uu_profileDataHit;
k_popMandatoryQueue;
}
+ transition({S, SM, O, OM, MM, MM_W, M, M_W}, Ifetch) {
+ h_load_hit;
+ uu_profileInstHit;
+ k_popMandatoryQueue;
+ }
+
+ // Transitions from Shared
transition(S, Store, SM) {
i_allocateTBE;
b_issueGETX;
- // uu_profileMiss;
+ uu_profileDataMiss;
k_popMandatoryQueue;
}
@@ -966,15 +982,10 @@
}
// Transitions from Owned
- transition({O, OM}, {Load, Ifetch}) {
- h_load_hit;
- k_popMandatoryQueue;
- }
-
transition(O, Store, OM) {
i_allocateTBE;
b_issueGETX;
- // uu_profileMiss;
+ uu_profileDataMiss;
k_popMandatoryQueue;
}
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