changeset f037e7b4a827 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f037e7b4a827
description:
ruby: moesi hammer: cosmetic changes
Updates copyright years, removes space at the end of lines, shortens
variable names.
diffstat:
configs/ruby/MOESI_hammer.py | 6 +-
src/mem/protocol/MOESI_hammer-cache.sm | 155 +++++++++++++++++---------------
2 files changed, 86 insertions(+), 75 deletions(-)
diffs (truncated from 525 to 300 lines):
diff -r 744fb905297c -r f037e7b4a827 configs/ruby/MOESI_hammer.py
--- a/configs/ruby/MOESI_hammer.py Tue May 21 11:32:38 2013 -0500
+++ b/configs/ruby/MOESI_hammer.py Tue May 21 11:32:45 2013 -0500
@@ -100,9 +100,9 @@
l1_cntrl = L1Cache_Controller(version = i,
cntrl_id = cntrl_count,
- L1IcacheMemory = l1i_cache,
- L1DcacheMemory = l1d_cache,
- L2cacheMemory = l2_cache,
+ L1Icache = l1i_cache,
+ L1Dcache = l1d_cache,
+ L2cache = l2_cache,
no_mig_atomic = not \
options.allow_atomic_migration,
send_evictions = (
diff -r 744fb905297c -r f037e7b4a827 src/mem/protocol/MOESI_hammer-cache.sm
--- a/src/mem/protocol/MOESI_hammer-cache.sm Tue May 21 11:32:38 2013 -0500
+++ b/src/mem/protocol/MOESI_hammer-cache.sm Tue May 21 11:32:45 2013 -0500
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
+ * Copyright (c) 1999-2013 Mark D. Hill and David A. Wood
* Copyright (c) 2009 Advanced Micro Devices, Inc.
* All rights reserved.
*
@@ -26,18 +26,18 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * AMD's contributions to the MOESI hammer protocol do not constitute an
+ * AMD's contributions to the MOESI hammer protocol do not constitute an
* endorsement of its similarity to any AMD products.
*
* Authors: Milo Martin
* Brad Beckmann
*/
-machine(L1Cache, "AMD Hammer-like protocol")
+machine(L1Cache, "AMD Hammer-like protocol")
: Sequencer * sequencer,
- CacheMemory * L1IcacheMemory,
- CacheMemory * L1DcacheMemory,
- CacheMemory * L2cacheMemory,
+ CacheMemory * L1Icache,
+ CacheMemory * L1Dcache,
+ CacheMemory * L2cache,
Cycles cache_response_latency = 10,
Cycles issue_latency = 2,
Cycles l2_cache_hit_latency = 10,
@@ -188,17 +188,17 @@
Cycles curCycle();
Entry getCacheEntry(Address address), return_by_pointer="yes" {
- Entry L2cache_entry := static_cast(Entry, "pointer",
L2cacheMemory.lookup(address));
+ Entry L2cache_entry := static_cast(Entry, "pointer",
L2cache.lookup(address));
if(is_valid(L2cache_entry)) {
return L2cache_entry;
}
- Entry L1Dcache_entry := static_cast(Entry, "pointer",
L1DcacheMemory.lookup(address));
+ Entry L1Dcache_entry := static_cast(Entry, "pointer",
L1Dcache.lookup(address));
if(is_valid(L1Dcache_entry)) {
return L1Dcache_entry;
}
- Entry L1Icache_entry := static_cast(Entry, "pointer",
L1IcacheMemory.lookup(address));
+ Entry L1Icache_entry := static_cast(Entry, "pointer",
L1Icache.lookup(address));
return L1Icache_entry;
}
@@ -217,17 +217,17 @@
}
Entry getL2CacheEntry(Address address), return_by_pointer="yes" {
- Entry L2cache_entry := static_cast(Entry, "pointer",
L2cacheMemory.lookup(address));
+ Entry L2cache_entry := static_cast(Entry, "pointer",
L2cache.lookup(address));
return L2cache_entry;
}
Entry getL1DCacheEntry(Address address), return_by_pointer="yes" {
- Entry L1Dcache_entry := static_cast(Entry, "pointer",
L1DcacheMemory.lookup(address));
+ Entry L1Dcache_entry := static_cast(Entry, "pointer",
L1Dcache.lookup(address));
return L1Dcache_entry;
}
Entry getL1ICacheEntry(Address address), return_by_pointer="yes" {
- Entry L1Icache_entry := static_cast(Entry, "pointer",
L1IcacheMemory.lookup(address));
+ Entry L1Icache_entry := static_cast(Entry, "pointer",
L1Icache.lookup(address));
return L1Icache_entry;
}
@@ -241,9 +241,9 @@
}
void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
- assert((L1DcacheMemory.isTagPresent(addr) &&
L1IcacheMemory.isTagPresent(addr)) == false);
- assert((L1IcacheMemory.isTagPresent(addr) &&
L2cacheMemory.isTagPresent(addr)) == false);
- assert((L1DcacheMemory.isTagPresent(addr) &&
L2cacheMemory.isTagPresent(addr)) == false);
+ assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) ==
false);
+ assert((L1Icache.isTagPresent(addr) && L2cache.isTagPresent(addr)) ==
false);
+ assert((L1Dcache.isTagPresent(addr) && L2cache.isTagPresent(addr)) ==
false);
if (is_valid(tbe)) {
tbe.TBEState := state;
@@ -293,7 +293,7 @@
//
// NOTE direct local hits should not call this
//
- return GenericMachineType:L1Cache_wCC;
+ return GenericMachineType:L1Cache_wCC;
} else {
return ConvertMachToGenericMach(machineIDToMachineType(sender));
}
@@ -304,7 +304,7 @@
cache_entry.FromL2 := false;
return GenericMachineType:L2Cache;
} else {
- return GenericMachineType:L1Cache;
+ return GenericMachineType:L1Cache;
}
}
@@ -380,7 +380,8 @@
Entry cache_entry := getCacheEntry(in_msg.Address);
TBE tbe := TBEs[in_msg.Address];
- if ((in_msg.Type == CoherenceRequestType:GETX) || (in_msg.Type ==
CoherenceRequestType:GETF)) {
+ if ((in_msg.Type == CoherenceRequestType:GETX) ||
+ (in_msg.Type == CoherenceRequestType:GETF)) {
trigger(Event:Other_GETX, in_msg.Address, cache_entry, tbe);
} else if (in_msg.Type == CoherenceRequestType:MERGED_GETS) {
trigger(Event:Merged_GETS, in_msg.Address, cache_entry, tbe);
@@ -428,7 +429,8 @@
Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
if (is_valid(L1Icache_entry)) {
- // The tag matches for the L1, so the L1 fetches the line. We
know it can't be in the L2 due to exclusion
+ // The tag matches for the L1, so the L1 fetches the line.
+ // We know it can't be in the L2 due to exclusion
trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress, L1Icache_entry, tbe);
} else {
@@ -436,18 +438,18 @@
Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
if (is_valid(L1Dcache_entry)) {
// The block is in the wrong L1, try to write it to the L2
- if (L2cacheMemory.cacheAvail(in_msg.LineAddress)) {
+ if (L2cache.cacheAvail(in_msg.LineAddress)) {
trigger(Event:L1_to_L2, in_msg.LineAddress, L1Dcache_entry,
tbe);
} else {
- Address l2_victim_addr :=
L2cacheMemory.cacheProbe(in_msg.LineAddress);
+ Address l2_victim_addr :=
L2cache.cacheProbe(in_msg.LineAddress);
trigger(Event:L2_Replacement,
- l2_victim_addr,
+ l2_victim_addr,
getL2CacheEntry(l2_victim_addr),
TBEs[l2_victim_addr]);
}
}
- if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) {
+ if (L1Icache.cacheAvail(in_msg.LineAddress)) {
// L1 does't have the line, but we have space for it in the L1
Entry L2cache_entry := getL2CacheEntry(in_msg.LineAddress);
@@ -462,15 +464,15 @@
}
} else {
// No room in the L1, so we need to make room
- Address l1i_victim_addr :=
L1IcacheMemory.cacheProbe(in_msg.LineAddress);
- if (L2cacheMemory.cacheAvail(l1i_victim_addr)) {
+ Address l1i_victim_addr :=
L1Icache.cacheProbe(in_msg.LineAddress);
+ if (L2cache.cacheAvail(l1i_victim_addr)) {
// The L2 has room, so we move the line from the L1 to the L2
trigger(Event:L1_to_L2,
l1i_victim_addr,
getL1ICacheEntry(l1i_victim_addr),
TBEs[l1i_victim_addr]);
} else {
- Address l2_victim_addr :=
L2cacheMemory.cacheProbe(l1i_victim_addr);
+ Address l2_victim_addr := L2cache.cacheProbe(l1i_victim_addr);
// The L2 does not have room, so we replace a line from the L2
trigger(Event:L2_Replacement,
l2_victim_addr,
@@ -484,7 +486,8 @@
Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
if (is_valid(L1Dcache_entry)) {
- // The tag matches for the L1, so the L1 fetches the line. We
know it can't be in the L2 due to exclusion
+ // The tag matches for the L1, so the L1 fetches the line.
+ // We know it can't be in the L2 due to exclusion
trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress, L1Dcache_entry, tbe);
} else {
@@ -493,10 +496,10 @@
Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
if (is_valid(L1Icache_entry)) {
// The block is in the wrong L1, try to write it to the L2
- if (L2cacheMemory.cacheAvail(in_msg.LineAddress)) {
+ if (L2cache.cacheAvail(in_msg.LineAddress)) {
trigger(Event:L1_to_L2, in_msg.LineAddress, L1Icache_entry,
tbe);
} else {
- Address l2_victim_addr :=
L2cacheMemory.cacheProbe(in_msg.LineAddress);
+ Address l2_victim_addr :=
L2cache.cacheProbe(in_msg.LineAddress);
trigger(Event:L2_Replacement,
l2_victim_addr,
getL2CacheEntry(l2_victim_addr),
@@ -504,7 +507,7 @@
}
}
- if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) {
+ if (L1Dcache.cacheAvail(in_msg.LineAddress)) {
// L1 does't have the line, but we have space for it in the L1
Entry L2cache_entry := getL2CacheEntry(in_msg.LineAddress);
if (is_valid(L2cache_entry)) {
@@ -518,15 +521,15 @@
}
} else {
// No room in the L1, so we need to make room
- Address l1d_victim_addr :=
L1DcacheMemory.cacheProbe(in_msg.LineAddress);
- if (L2cacheMemory.cacheAvail(l1d_victim_addr)) {
+ Address l1d_victim_addr :=
L1Dcache.cacheProbe(in_msg.LineAddress);
+ if (L2cache.cacheAvail(l1d_victim_addr)) {
// The L2 has room, so we move the line from the L1 to the L2
trigger(Event:L1_to_L2,
l1d_victim_addr,
getL1DCacheEntry(l1d_victim_addr),
TBEs[l1d_victim_addr]);
} else {
- Address l2_victim_addr :=
L2cacheMemory.cacheProbe(l1d_victim_addr);
+ Address l2_victim_addr := L2cache.cacheProbe(l1d_victim_addr);
// The L2 does not have room, so we replace a line from the L2
trigger(Event:L2_Replacement,
l2_victim_addr,
@@ -539,7 +542,7 @@
}
}
}
-
+
// ACTIONS
action(a_issueGETS, "a", desc="Issue GETS") {
@@ -551,7 +554,9 @@
out_msg.Destination.add(map_Address_to_Directory(address));
out_msg.MessageSize := MessageSizeType:Request_Control;
out_msg.InitialRequestTime := curCycle();
- tbe.NumPendingMsgs := machineCount(MachineType:L1Cache); // One from
each other cache (n-1) plus the memory (+1)
+
+ // One from each other cache (n-1) plus the memory (+1)
+ tbe.NumPendingMsgs := machineCount(MachineType:L1Cache);
}
}
@@ -564,7 +569,9 @@
out_msg.Destination.add(map_Address_to_Directory(address));
out_msg.MessageSize := MessageSizeType:Request_Control;
out_msg.InitialRequestTime := curCycle();
- tbe.NumPendingMsgs := machineCount(MachineType:L1Cache); // One from
each other cache (n-1) plus the memory (+1)
+
+ // One from each other cache (n-1) plus the memory (+1)
+ tbe.NumPendingMsgs := machineCount(MachineType:L1Cache);
}
}
@@ -580,7 +587,9 @@
out_msg.InitialRequestTime := curCycle();
}
}
- tbe.NumPendingMsgs := machineCount(MachineType:L1Cache); // One from each
other cache (n-1) plus the memory (+1)
+
+ // One from each other cache (n-1) plus the memory (+1)
+ tbe.NumPendingMsgs := machineCount(MachineType:L1Cache);
}
action(bf_issueGETF, "bf", desc="Issue GETF") {
@@ -592,7 +601,9 @@
out_msg.Destination.add(map_Address_to_Directory(address));
out_msg.MessageSize := MessageSizeType:Request_Control;
out_msg.InitialRequestTime := curCycle();
- tbe.NumPendingMsgs := machineCount(MachineType:L1Cache); // One from
each other cache (n-1) plus the memory (+1)
+
+ // One from each other cache (n-1) plus the memory (+1)
+ tbe.NumPendingMsgs := machineCount(MachineType:L1Cache);
}
}
@@ -752,7 +763,7 @@
}
}
}
-
+
action(emt_sendDataSharedMultipleFromTBE, "emt", desc="Send data from tbe to
all requestors") {
peek(forwardToCache_in, RequestMsg) {
enqueue(responseNetwork_out, ResponseMsg,
latency=cache_response_latency) {
@@ -852,7 +863,7 @@
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
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