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(Updated May 24, 2013, 10:05 a.m.) Review request for Default. Description ------- This patch adds the possibility to integrate a snoop filter in coherent bus. Only one snoop filter per system is allowed. The snoop_filter is a new base class, which, depending on a paramenter, is instantiated in coherent bus. SnoopFilter(1): The snoop filter interface is composed by the only method interrogateAndUpdate, When a pkt is received, the snoop filter returns the snoop_value. For cacheable allocate transactions from snooping masters, it updates/inserts the snoop_value. SnoopFilterDir(2): Within the snoop filter class, an additional base class snoop_filter_dir controls the directory structure of the snoop filter (similar to a cache in its organization). Current selectable replacement policy are Random and LRU. Its interface is composed by: findAddress: it returns the snoop_value for a given address. snoop value = 0 means miss Update: it updates the snoop value for a given address and way Insert: it inserts a snoop value for a miss. However, in case the set is full, the replaced line cause a backinvalidation, which means the corresponding data in CPU caches must be invalidated (and written back if dirty). Backinvalidation is controlled by the additional base class backinvalidation_buffer BackInvalidateBuffer (5): Every time a cache is evicted from the snoop filter, a new item is created in the back invalidate buffer (inside the method Insert of SnoopFilterDir). Its interface is composed of: hasAddress: to check if an address is contained in it eraseInfo: to delete an address from the buffer (backinvalidation sent and completed) pushBackInfo: to add an address in the buffer (line evicted from snoop filter dir) CoherenBus modifications (4): If the snoop filter is instantiated, every cacheable transaction in recvAtomic, is first compared against the snoop filter through interrogateAndUpdate method. Then, until the backinvalidate buffer is empty, backinvalidation are sent to the caches through forwardAtomic, accoording to a stored snoop value stored in the buffer. Finally, forwardAtomic snoops all the snooping masters according to the snoop_value returned by the snoop filter. Cache_impl modifications (5): The main modifications are related the support of backinvalidion packet and clean evict. Backinvalidation pkt, when received, cause the cache line to be invalidated (if hit) and written back (if dirty). Also when a dirty backinvalidation happens in L1, the line has to be written back to main memory, passing thorugh L2. CleanEvict are pkt generated when a clean line is replaced in the cache. For both pkts, and for additional stats, L2 has to behave "inclusive" of L1s: by that it means that if a line is written back from L2 to main memory, no L1s has to contain the data. Similartly, clean evicts from L2 to main memory must be sent only if that line is contained only in L2. Other modifications (6): Additional packets (Snoop Filter <-> caches) Backinvalidation and CleanEvict have been added. Also the packet IsDataInCache, to This patch works only in atomic mode. Some modifications to timing mode have been implemented, but not tested. Timing mode is work in progress Diffs ----- src/mem/Bus.py 2b827990de88dcf80a4720eec10cef3971a76f25 src/mem/SConscript 2b827990de88dcf80a4720eec10cef3971a76f25 src/mem/cache/BaseCache.py 2b827990de88dcf80a4720eec10cef3971a76f25 src/mem/cache/base.hh 2b827990de88dcf80a4720eec10cef3971a76f25 src/mem/cache/base.cc 2b827990de88dcf80a4720eec10cef3971a76f25 src/mem/cache/cache_impl.hh 2b827990de88dcf80a4720eec10cef3971a76f25 src/mem/coherent_bus.hh 2b827990de88dcf80a4720eec10cef3971a76f25 src/mem/coherent_bus.cc 2b827990de88dcf80a4720eec10cef3971a76f25 src/mem/packet.hh 2b827990de88dcf80a4720eec10cef3971a76f25 src/mem/packet.cc 2b827990de88dcf80a4720eec10cef3971a76f25 src/mem/request.hh 2b827990de88dcf80a4720eec10cef3971a76f25 src/mem/snoop_filter.hh PRE-CREATION src/mem/snoop_filter.cc PRE-CREATION src/mem/snoop_filter_dir.hh PRE-CREATION src/mem/snoop_filter_dir.cc PRE-CREATION Diff: http://reviews.gem5.org/r/1884/diff/ Testing ------- Various simulations with different paramters Thanks, Michele Riga _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
