changeset 353587055aff in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=353587055aff
description:
x86: Fix the flag handling code in FABS and FCHS
This changeset fixes two problems in the FABS and FCHS
implementation. First, the ISA parser expects the assignment in
flag_code to be a pure assignment and not an and-assignment, which
leads to the isa_parser omitting the misc reg update. Second, the FCHS
and FABS macro-ops don't set the SetStatus flag, which means that the
default micro-op version, which doesn't update FSW, is executed.
diffstat:
src/arch/x86/isa/insts/x87/arithmetic/change_sign.py | 4 ++--
src/arch/x86/isa/microops/fpop.isa | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diffs (31 lines):
diff -r 2f0cecb37686 -r 353587055aff
src/arch/x86/isa/insts/x87/arithmetic/change_sign.py
--- a/src/arch/x86/isa/insts/x87/arithmetic/change_sign.py Sun Jun 16
08:27:42 2013 -0500
+++ b/src/arch/x86/isa/insts/x87/arithmetic/change_sign.py Tue Jun 18
16:10:21 2013 +0200
@@ -38,10 +38,10 @@
microcode = '''
def macroop FABS {
- absfp st(0), st(0)
+ absfp st(0), st(0), SetStatus=True
};
def macroop FCHS {
- chsfp st(0), st(0)
+ chsfp st(0), st(0), SetStatus=True
};
'''
diff -r 2f0cecb37686 -r 353587055aff src/arch/x86/isa/microops/fpop.isa
--- a/src/arch/x86/isa/microops/fpop.isa Sun Jun 16 08:27:42 2013 -0500
+++ b/src/arch/x86/isa/microops/fpop.isa Tue Jun 18 16:10:21 2013 +0200
@@ -365,9 +365,9 @@
class absfp(FpUnaryOp):
code = 'FpDestReg = fabs(FpSrcReg1);'
- flag_code = 'FSW &= (~CC1Bit);'
+ flag_code = 'FSW = FSW & (~CC1Bit);'
class chsfp(FpUnaryOp):
code = 'FpDestReg = (-1) * (FpSrcReg1);'
- flag_code = 'FSW &= (~CC1Bit);'
+ flag_code = 'FSW = FSW & (~CC1Bit);'
}};
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