----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1927/ -----------------------------------------------------------
(Updated June 24, 2013, 5:53 a.m.) Review request for Default. Changes ------- Updates: - a burst length in beats for each memory type. - an interface width for each memory type. - the memory controller model is extended to reason about "system" packets vs "dram" packets and assemble the responses properly. It means that system packets larger than a full burst are split into multiple dram packets. Repository: gem5 Description ------- This patch gets rid of bytesPerCacheLine parameter and makes the DRAM configuration separate from cache line size. Instead of bytesPerCacheLine, I define a parameter for DRAM called burst_length. The burst_length parameter shows the size of a DRAM burst in bytes and is 64 bytes for all current DRAM configurations. Note, this parameter is coupled with tBURST. Also, I replace lines_per_rowbuffer with bursts_per_rowbuffer, because lines_per_rowbuffer is defined based on 64-byte cache lines which makes the code unportable. Next patch could be to add support for requests larger than burst length. Diffs (updated) ----- src/mem/simple_dram.cc UNKNOWN src/mem/simple_dram.hh UNKNOWN src/mem/SimpleDRAM.py UNKNOWN Diff: http://reviews.gem5.org/r/1927/diff/ Testing ------- None Thanks, Amin Farmahini _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev