changeset 5558ee8dd7d9 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=5558ee8dd7d9
description:
config: Remove redundant explicit setting of default clocks
This patch removes the explicit setting of the clock period for
certain instances of CoherentBus, NonCoherentBus and IOCache where the
specified clock is same as the default value of the system clock. As
all the values used are the defaults, there are no performance
changes. There are similar cases where the toL2Bus is set to use the
parent CPU clock which is already the default behaviour.
The main motivation for these simplifications is to ease the
introduction of clock domains.
diffstat:
configs/example/fs.py | 4 ++--
src/cpu/BaseCPU.py | 8 ++++----
src/dev/CopyEngine.py | 2 --
src/dev/arm/RealView.py | 2 --
src/mem/ruby/system/RubySystem.py | 1 -
tests/configs/base_config.py | 4 ++--
tests/configs/memtest.py | 2 +-
tests/configs/tgen-simple-dram.py | 2 +-
tests/configs/tgen-simple-mem.py | 2 +-
9 files changed, 11 insertions(+), 16 deletions(-)
diffs (117 lines):
diff -r 562bb3ea2b69 -r 5558ee8dd7d9 configs/example/fs.py
--- a/configs/example/fs.py Thu Jun 27 05:49:49 2013 -0400
+++ b/configs/example/fs.py Thu Jun 27 05:49:49 2013 -0400
@@ -134,8 +134,8 @@
test_sys.vm = KvmVM()
if options.caches or options.l2cache:
- test_sys.iocache = IOCache(clock = '1GHz',
- addr_ranges = test_sys.mem_ranges)
+ # By default the IOCache runs at the system clock
+ test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
test_sys.iocache.cpu_side = test_sys.iobus.master
test_sys.iocache.mem_side = test_sys.membus.slave
else:
diff -r 562bb3ea2b69 -r 5558ee8dd7d9 src/cpu/BaseCPU.py
--- a/src/cpu/BaseCPU.py Thu Jun 27 05:49:49 2013 -0400
+++ b/src/cpu/BaseCPU.py Thu Jun 27 05:49:49 2013 -0400
@@ -281,10 +281,10 @@
def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
- # Override the default bus clock of 1 GHz and uses the CPU
- # clock for the L1-to-L2 bus, and also set a width of 32 bytes
- # (256-bits), which is four times that of the default bus.
- self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32)
+ # Set a width of 32 bytes (256-bits), which is four times that
+ # of the default bus. The clock of the CPU is inherited by
+ # default.
+ self.toL2Bus = CoherentBus(width = 32)
self.connectCachedPorts(self.toL2Bus)
self.l2cache = l2c
self.toL2Bus.master = self.l2cache.cpu_side
diff -r 562bb3ea2b69 -r 5558ee8dd7d9 src/dev/CopyEngine.py
--- a/src/dev/CopyEngine.py Thu Jun 27 05:49:49 2013 -0400
+++ b/src/dev/CopyEngine.py Thu Jun 27 05:49:49 2013 -0400
@@ -53,8 +53,6 @@
ChanCnt = Param.UInt8(4, "Number of DMA channels that exist on device")
XferCap = Param.MemorySize('4kB', "Number of bits of transfer size that
are supported")
- # Override the default clock
- clock = '500MHz'
latBeforeBegin = Param.Latency('20ns', "Latency after a DMA command is
seen before it's proccessed")
latAfterCompletion = Param.Latency('20ns', "Latency after a DMA command is
complete before it's reported as such")
diff -r 562bb3ea2b69 -r 5558ee8dd7d9 src/dev/arm/RealView.py
--- a/src/dev/arm/RealView.py Thu Jun 27 05:49:49 2013 -0400
+++ b/src/dev/arm/RealView.py Thu Jun 27 05:49:49 2013 -0400
@@ -118,8 +118,6 @@
gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to
GIC")
- # Override the default clock
- clock = '1GHz'
class PL031(AmbaIntDevice):
type = 'PL031'
diff -r 562bb3ea2b69 -r 5558ee8dd7d9 src/mem/ruby/system/RubySystem.py
--- a/src/mem/ruby/system/RubySystem.py Thu Jun 27 05:49:49 2013 -0400
+++ b/src/mem/ruby/system/RubySystem.py Thu Jun 27 05:49:49 2013 -0400
@@ -36,7 +36,6 @@
random_seed = Param.Int(1234, "random seed used by the simulation");
randomization = Param.Bool(False,
"insert random delays on message enqueue times");
- clock = '1GHz'
block_size_bytes = Param.UInt32(64,
"default cache block size; must be a power of two");
mem_size = Param.MemorySize("total memory size of the system");
diff -r 562bb3ea2b69 -r 5558ee8dd7d9 tests/configs/base_config.py
--- a/tests/configs/base_config.py Thu Jun 27 05:49:49 2013 -0400
+++ b/tests/configs/base_config.py Thu Jun 27 05:49:49 2013 -0400
@@ -161,8 +161,8 @@
def init_system(self, system):
BaseSystem.init_system(self, system)
- #create the iocache
- system.iocache = IOCache(clock='1GHz', addr_ranges=system.mem_ranges)
+ # create the iocache, which by default runs at the system clock
+ system.iocache = IOCache(addr_ranges=system.mem_ranges)
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
diff -r 562bb3ea2b69 -r 5558ee8dd7d9 tests/configs/memtest.py
--- a/tests/configs/memtest.py Thu Jun 27 05:49:49 2013 -0400
+++ b/tests/configs/memtest.py Thu Jun 27 05:49:49 2013 -0400
@@ -39,7 +39,7 @@
system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
funcbus = NoncoherentBus(),
physmem = SimpleMemory(),
- membus = CoherentBus(clock="1GHz", width=16))
+ membus = CoherentBus(width=16))
# l2cache & bus
system.toL2Bus = CoherentBus(clock="2GHz", width=16)
diff -r 562bb3ea2b69 -r 5558ee8dd7d9 tests/configs/tgen-simple-dram.py
--- a/tests/configs/tgen-simple-dram.py Thu Jun 27 05:49:49 2013 -0400
+++ b/tests/configs/tgen-simple-dram.py Thu Jun 27 05:49:49 2013 -0400
@@ -49,7 +49,7 @@
# system simulated
system = System(cpu = cpu, physmem = DDR3_1600_x64(),
- membus = NoncoherentBus(clock="1GHz", width = 16))
+ membus = NoncoherentBus(width = 16))
# add a communication monitor
system.monitor = CommMonitor()
diff -r 562bb3ea2b69 -r 5558ee8dd7d9 tests/configs/tgen-simple-mem.py
--- a/tests/configs/tgen-simple-mem.py Thu Jun 27 05:49:49 2013 -0400
+++ b/tests/configs/tgen-simple-mem.py Thu Jun 27 05:49:49 2013 -0400
@@ -49,7 +49,7 @@
# system simulated
system = System(cpu = cpu, physmem = SimpleMemory(),
- membus = NoncoherentBus(clock="1GHz", width = 16))
+ membus = NoncoherentBus(width = 16))
# add a communication monitor, and also trace all the packets
system.monitor = CommMonitor(trace_file = "monitor.ptrc.gz")
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