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Review request for Default. Repository: gem5 Description ------- Changeset 9815:b4345df24f02 --------------------------- mem: Set the cache line size on a system level This patch removes the notion of a peer block size and instead sets the cache line size on the system level. Previously the size was set per cache, and communicated through the interconnect. There were plenty checks to ensure that everyone had the same size specified, and these checks are now removed. Another benefit that is not yet harnessed is that the cache line size is now known at construction time, rather than after the port binding. Hence, the block size can be locally stored and does not have to be queried every time it is used. A follow-on patch updates the configuration scripts accordingly. Diffs ----- src/arch/arm/isa.cc 13ffc0066b76 src/cpu/base.hh 13ffc0066b76 src/cpu/base.cc 13ffc0066b76 src/cpu/base_dyn_inst.hh 13ffc0066b76 src/cpu/checker/cpu.cc 13ffc0066b76 src/cpu/inorder/resources/cache_unit.cc 13ffc0066b76 src/cpu/o3/fetch.hh 13ffc0066b76 src/cpu/o3/fetch_impl.hh 13ffc0066b76 src/cpu/o3/lsq_unit_impl.hh 13ffc0066b76 src/cpu/simple/atomic.cc 13ffc0066b76 src/cpu/simple/timing.cc 13ffc0066b76 src/cpu/testers/memtest/memtest.cc 13ffc0066b76 src/cpu/testers/traffic_gen/traffic_gen.cc 13ffc0066b76 src/cpu/thread_state.cc 13ffc0066b76 src/dev/dma_device.hh 13ffc0066b76 src/dev/dma_device.cc 13ffc0066b76 src/mem/Bus.py 13ffc0066b76 src/mem/SimpleDRAM.py 13ffc0066b76 src/mem/addr_mapper.hh 13ffc0066b76 src/mem/addr_mapper.cc 13ffc0066b76 src/mem/bridge.cc 13ffc0066b76 src/mem/bus.hh 13ffc0066b76 src/mem/bus.cc 13ffc0066b76 src/mem/cache/BaseCache.py 13ffc0066b76 src/mem/cache/base.cc 13ffc0066b76 src/mem/cache/cache.hh 13ffc0066b76 src/mem/cache/tags/Tags.py 13ffc0066b76 src/mem/coherent_bus.hh 13ffc0066b76 src/mem/comm_monitor.hh 13ffc0066b76 src/mem/comm_monitor.cc 13ffc0066b76 src/mem/fs_translating_port_proxy.hh 13ffc0066b76 src/mem/fs_translating_port_proxy.cc 13ffc0066b76 src/mem/noncoherent_bus.hh 13ffc0066b76 src/mem/port.hh 13ffc0066b76 src/mem/port.cc 13ffc0066b76 src/mem/port_proxy.hh 13ffc0066b76 src/mem/port_proxy.cc 13ffc0066b76 src/mem/ruby/system/RubyPort.hh 13ffc0066b76 src/mem/ruby/system/RubyPort.cc 13ffc0066b76 src/mem/se_translating_port_proxy.cc 13ffc0066b76 src/mem/simple_dram.cc 13ffc0066b76 src/sim/System.py 13ffc0066b76 src/sim/system.hh 13ffc0066b76 src/sim/system.cc 13ffc0066b76 Diff: http://reviews.gem5.org/r/1948/diff/ Testing ------- All regressions pass Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
