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This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/1826/
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(Updated July 18, 2013, 7:37 p.m.)
Review request for Default.
Repository: gem5
Description (updated)
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Changeset 9819:82757d5512bb
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mem: add retry mechanism for cache fills in classic cache model
The changeset 6122d201ff80 modeled the cache bank and blocks the cache access
if the target bank is busy. However, due to the lack of retry mechanism at the
cache master port, that changeset cannot properly blocks the cache traffic that
is towards CPU.
This patch modifies the CoherentBus model and adds a flow control scheme to the
RespLayer. With this modification, cache fill operations can now be properly
modeled.
@todo The modification to CoherentBus is a little hacky. e.g. The recvRetry
functions for Req and Resp are not symmetric
@todo Might also need to modify noncoherent bus
@todo There is no write buffer entries for cache fill operations. An
incremental patch will be needed to model the cache fill buffer
Diffs (updated)
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src/mem/cache/base.hh 3b3b94536547
src/mem/cache/cache_impl.hh 3b3b94536547
src/mem/coherent_bus.hh 3b3b94536547
src/mem/coherent_bus.cc 3b3b94536547
Diff: http://reviews.gem5.org/r/1826/diff/
Testing
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Thanks,
Xiangyu Dong
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