> On Aug. 27, 2013, 3:06 p.m., Nilay Vaish wrote: > > At some point of time, I was planning to add branch predictor state > > to the checkpoint. Typically, we create checkpoint using the atomic > > or the simple timing cpu. Therefore, I had added branch predictor > > to the base cpu. > > Andreas Hansson wrote: > Perhaps I'm missing something, but if it is always null for these CPUs, > then there won't be any state to restore anyways. Right?
As this is needed for the NULL ISA patches, I'd be very keen to see this go out as is for now. If there are reasons to change things at a later stage, then let's worry about it when we get to that point. Ok? - Andreas ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1976/#review4644 ----------------------------------------------------------- On Aug. 19, 2013, 9:38 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1976/ > ----------------------------------------------------------- > > (Updated Aug. 19, 2013, 9:38 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 9845:73704b98a61d > --------------------------- > cpu: Move the branch predictor out of the BaseCPU > > The branch predictor is guarded by having either the in-order or > out-of-order CPU as one of the available CPU models and therefore > should not be used in the BaseCPU. This patch moves the parameter to > the relevant CPU classes. > > > Diffs > ----- > > src/cpu/BaseCPU.py 43d22d746e7a > src/cpu/inorder/InOrderCPU.py 43d22d746e7a > src/cpu/o3/O3CPU.py 43d22d746e7a > > Diff: http://reviews.gem5.org/r/1976/diff/ > > > Testing > ------- > > All regressions pass > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
