> On Aug. 27, 2013, 8:43 a.m., Nilay Vaish wrote: > > src/cpu/o3/cpu.cc, line 972 > > <http://reviews.gem5.org/r/1988/diff/1/?file=37283#file37283line972> > > > > Do we use this code? From a cursory look, it seems that this code is > > required for context switching in SE mode. Should we not just drop all of > > it?
I don't believe we use this code, and I don't believe it works properly. What it is supposed to do is to dynamically change the number of thread contexts so that if there's only one active thread, it uses all the resources (including all the physical registers), then as you add threads you allocate from the physical register file to accommodate them. Currently I believe that you statically set the number of threads, and then each thread gets a set of physical registers to hold its architectural registers, then they only compete for the leftover physical regs. I would not be opposed to identifying all the unused code and getting rid of it. However, that should be done in a separate changeset. - Steve ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1988/#review4651 ----------------------------------------------------------- On Aug. 21, 2013, 5:41 p.m., Steve Reinhardt wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1988/ > ----------------------------------------------------------- > > (Updated Aug. 21, 2013, 5:41 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 9851:27064c03d2c8 > --------------------------- > cpu: add a condition-code register class > > Add a third register class for condition codes, > in parallel with the integer and FP classes. > No ISAs use the CC class at this point though. > > > Diffs > ----- > > src/arch/SConscript 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/arch/alpha/isa.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/arch/alpha/registers.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/arch/alpha/utility.cc 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/arch/arm/insts/static_inst.cc 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/arch/arm/isa.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/arch/arm/registers.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/arch/arm/utility.cc 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/arch/isa_parser.py 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/arch/mips/isa.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/arch/mips/registers.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/arch/power/insts/static_inst.cc > 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/arch/power/isa.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/arch/power/registers.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/arch/power/utility.cc 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/arch/sparc/isa.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/arch/sparc/registers.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/arch/sparc/utility.cc 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/arch/x86/insts/static_inst.cc 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/arch/x86/isa.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/arch/x86/registers.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/arch/x86/utility.cc 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/base_dyn_inst.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/checker/cpu.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/checker/cpu_impl.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/checker/thread_context.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/inorder/cpu.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/inorder/cpu.cc 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/inorder/inorder_dyn_inst.hh > 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/inorder/inorder_dyn_inst.cc > 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/inorder/thread_context.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/inorder/thread_context.cc 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/o3/O3CPU.py 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/o3/cpu.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/o3/cpu.cc 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/o3/dyn_inst.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/o3/free_list.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/o3/free_list.cc 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/o3/inst_queue.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/o3/inst_queue_impl.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/o3/regfile.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/o3/regfile.cc PRE-CREATION > src/cpu/o3/rename_impl.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/o3/rename_map.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/o3/rename_map.cc 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/o3/thread_context.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/o3/thread_context_impl.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/ozone/cpu_impl.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/reg_class.hh PRE-CREATION > src/cpu/reg_class.cc PRE-CREATION > src/cpu/simple/base.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/simple/base.cc 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/simple_thread.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/static_inst.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/thread_context.hh 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > src/cpu/thread_context.cc 1ddfb0679c7569fb56382ac2187d6de038fd6f28 > > Diff: http://reviews.gem5.org/r/1988/diff/ > > > Testing > ------- > > > Thanks, > > Steve Reinhardt > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
