> On Oct. 3, 2013, 4:59 p.m., Ali Saidi wrote:
> > This isn't actually true. the ASI bits are overloaded for ARM at least
>
> Andreas Sandberg wrote:
> From my digging, it seems like ARM uses the _asid field
> (getAsid()/setAsid()) in request. As far as I can tell, the ASID is set in
> the tlb, but there are never any calls to getAsid() anywhere in the code
> base, so this seems unused at the moment. SPARC on the other hand uses the
> ASI bits int the Flags field to represent, which is not used by any other ISA.
>
> Are you sure that you are not confusing the ASID field and the ASI bits
> of the flags field?
>
> (A related question -- why do we store ASIDs in two different places?)
See my previous email on ASID != ASI.
The ARM loads/stores use the ASI bits in the request to pass alignment
requirements and other such requirements to the TLB:
See:
arch/arm/tlb.hh:~71
enum ArmFlags {
AlignmentMask = 0x7,
....
MustBeOne = 0x40
};
- Ali
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/2032/#review4763
-----------------------------------------------------------
On Oct. 3, 2013, 1:21 p.m., Andreas Sandberg wrote:
>
> -----------------------------------------------------------
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/2032/
> -----------------------------------------------------------
>
> (Updated Oct. 3, 2013, 1:21 p.m.)
>
>
> Review request for Default.
>
>
> Repository: gem5
>
>
> Description
> -------
>
> Changeset 9905:2f0374a09fc5
> ---------------------------
> arch: Use ASI 0xFF instead of bit 63 to for generic IPRs
>
> Using address bit 63 to identify generic IPRs caused problems on
> SPARC, where IPRs are heavily used. This changeset redefines how
> generic IPRs are identified. Instead of using bit 63, we now use the
> ASI field in a request. We reserve ASI 0xFF for internal gem5 use. ASI
> 0xFF is implementation defined on SPARC, which means that we can
> safely use it for generic IPRs. No other architecture is currently
> using the ASI field.
>
>
> Diffs
> -----
>
> src/arch/generic/mmapped_ipr.hh e672a39fd426
> src/arch/sparc/asi.hh e672a39fd426
> src/arch/x86/tlb.cc e672a39fd426
>
> Diff: http://reviews.gem5.org/r/2032/diff/
>
>
> Testing
> -------
>
> m5ops using the IPR interface works on x86 in kvm. ARM, SPARC, and x86
> targets compile. Can't run the affected (80.solaris-boot) test case due to
> missing binaries.
>
>
> Thanks,
>
> Andreas Sandberg
>
>
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
