changeset 44ef5ed3aee0 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=44ef5ed3aee0
description:
cpu: Fix Checker register index use
This patch fixes an issue in the checker CPU register indexing. The
code will not even compile using LTO as deep inlining causes the used
index to be outside the array bounds.
diffstat:
src/cpu/checker/cpu_impl.hh | 8 ++++----
1 files changed, 4 insertions(+), 4 deletions(-)
diffs (29 lines):
diff -r cc02ad629b36 -r 44ef5ed3aee0 src/cpu/checker/cpu_impl.hh
--- a/src/cpu/checker/cpu_impl.hh Thu Nov 14 15:03:42 2013 -0800
+++ b/src/cpu/checker/cpu_impl.hh Fri Nov 15 03:47:10 2013 -0500
@@ -607,10 +607,10 @@
thread->setIntReg(idx, mismatch_val);
break;
case FloatRegClass:
- thread->setFloatRegBits(idx, mismatch_val);
+ thread->setFloatRegBits(idx - TheISA::FP_Reg_Base, mismatch_val);
break;
case CCRegClass:
- thread->setCCReg(idx, mismatch_val);
+ thread->setCCReg(idx - TheISA::CC_Reg_Base, mismatch_val);
break;
case MiscRegClass:
thread->setMiscReg(idx - TheISA::Misc_Reg_Base,
@@ -628,10 +628,10 @@
thread->setIntReg(idx, res);
break;
case FloatRegClass:
- thread->setFloatRegBits(idx, res);
+ thread->setFloatRegBits(idx - TheISA::FP_Reg_Base, res);
break;
case CCRegClass:
- thread->setCCReg(idx, res);
+ thread->setCCReg(idx - TheISA::CC_Reg_Base, res);
break;
case MiscRegClass:
// Try to get the proper misc register index for ARM here...
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