changeset 2cce74fe359e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=2cce74fe359e
description:
sim: simulate with multiple threads and event queues
This patch adds support for simulating with multiple threads, each of
which operates on an event queue. Each sim object specifies which
eventq
is would like to be on. A custom barrier implementation is being added
using which eventqs synchronize.
The patch was tested in two different configurations:
1. ruby_network_test.py: in this simulation L1 cache controllers receive
requests from the cpu. The requests are replied to immediately
without
any communication taking place with any other level.
2. twosys-tsunami-simple-atomic: this configuration simulates a
client-server
system which are connected by an ethernet link.
We still lack the ability to communicate using message buffers or
ports. But
other things like simulation start and end, synchronizing after every
quantum
are working.
Committed by: Nilay Vaish
diffstat:
src/base/barrier.hh | 82 ++++++++++++
src/cpu/base.cc | 6 +-
src/cpu/kvm/base.cc | 3 +-
src/dev/etherlink.cc | 9 +-
src/dev/x86/Pc.py | 3 +-
src/python/m5/SimObject.py | 23 +-
src/python/m5/event.py | 12 +-
src/python/m5/main.py | 4 +
src/python/m5/simulate.py | 13 +-
src/python/swig/event.i | 12 +-
src/sim/Root.py | 11 +-
src/sim/SConscript | 1 +
src/sim/core.cc | 2 +
src/sim/core.hh | 4 +-
src/sim/debug.cc | 16 +-
src/sim/eventq.cc | 67 ++++++++-
src/sim/eventq.hh | 301 ++++++++++++++++++++++++++++----------------
src/sim/eventq_impl.hh | 28 ++-
src/sim/global_event.cc | 166 ++++++++++++++++++++++++
src/sim/global_event.hh | 230 ++++++++++++++++++++++++++++++++++
src/sim/root.cc | 2 +
src/sim/serialize.cc | 17 +-
src/sim/serialize.hh | 1 +
src/sim/sim_events.cc | 94 ++++++++-----
src/sim/sim_events.hh | 41 ++++-
src/sim/sim_exit.hh | 2 -
src/sim/sim_object.cc | 2 +-
src/sim/simulate.cc | 161 ++++++++++++++++++++---
src/sim/simulate.hh | 2 +-
src/sim/stat_control.cc | 25 ++-
30 files changed, 1087 insertions(+), 253 deletions(-)
diffs (truncated from 2087 to 300 lines):
diff -r b2bfc23f932c -r 2cce74fe359e src/base/barrier.hh
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/base/barrier.hh Mon Nov 25 11:21:00 2013 -0600
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2013 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+#ifndef __BASE_BARRIER_HH__
+#define __BASE_BARRIER_HH__
+
+#include <condition_variable>
+
+class Barrier
+{
+ private:
+ /// Mutex to protect access to numLeft and generation
+ std::mutex bMutex;
+ /// Condition variable for waiting on barrier
+ std::condition_variable bCond;
+ /// Number of threads we should be waiting for before completing the
barrier
+ unsigned numWaiting;
+ /// Generation of this barrier
+ unsigned generation;
+ /// Number of threads remaining for the current generation
+ unsigned numLeft;
+
+ public:
+ Barrier(unsigned _numWaiting)
+ : numWaiting(_numWaiting), generation(0), numLeft(_numWaiting)
+ {}
+
+ bool
+ wait()
+ {
+ std::unique_lock<std::mutex> lock(bMutex);
+ unsigned int gen = generation;
+
+ if (--numLeft == 0) {
+ generation++;
+ numLeft = numWaiting;
+ bCond.notify_all();
+ return true;
+ }
+ while (gen == generation)
+ bCond.wait(lock);
+ return false;
+ }
+};
+
+#endif // __BASE_BARRIER_HH__
diff -r b2bfc23f932c -r 2cce74fe359e src/cpu/base.cc
--- a/src/cpu/base.cc Fri Nov 15 13:21:15 2013 -0500
+++ b/src/cpu/base.cc Mon Nov 25 11:21:00 2013 -0600
@@ -13,6 +13,8 @@
*
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* Copyright (c) 2011 Regents of the University of California
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
+ * Copyright (c) 2013 Mark D. Hill and David A. Wood
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -569,7 +571,7 @@
BaseCPU::scheduleInstStop(ThreadID tid, Counter insts, const char *cause)
{
const Tick now(comInstEventQueue[tid]->getCurTick());
- Event *event(new SimLoopExitEvent(cause, 0));
+ Event *event(new LocalSimLoopExitEvent(cause, 0));
comInstEventQueue[tid]->schedule(event, now + insts);
}
@@ -578,7 +580,7 @@
BaseCPU::scheduleLoadStop(ThreadID tid, Counter loads, const char *cause)
{
const Tick now(comLoadEventQueue[tid]->getCurTick());
- Event *event(new SimLoopExitEvent(cause, 0));
+ Event *event(new LocalSimLoopExitEvent(cause, 0));
comLoadEventQueue[tid]->schedule(event, now + loads);
}
diff -r b2bfc23f932c -r 2cce74fe359e src/cpu/kvm/base.cc
--- a/src/cpu/kvm/base.cc Fri Nov 15 13:21:15 2013 -0500
+++ b/src/cpu/kvm/base.cc Mon Nov 25 11:21:00 2013 -0600
@@ -506,7 +506,8 @@
case RunningServiceCompletion:
case Running: {
- Tick ticksToExecute(mainEventQueue.nextTick() - curTick());
+ EventQueue *q = curEventQueue();
+ Tick ticksToExecute(q->nextTick() - curTick());
// We might need to update the KVM state.
syncKvmState();
diff -r b2bfc23f932c -r 2cce74fe359e src/dev/etherlink.cc
--- a/src/dev/etherlink.cc Fri Nov 15 13:21:15 2013 -0500
+++ b/src/dev/etherlink.cc Mon Nov 25 11:21:00 2013 -0600
@@ -142,7 +142,9 @@
void process();
virtual void serialize(ostream &os);
- virtual void unserialize(Checkpoint *cp, const string §ion);
+ void unserialize(Checkpoint *cp, const string §ion) {}
+ void unserialize(Checkpoint *cp, const string §ion,
+ EventQueue *eventq);
static Serializable *createForUnserialize(Checkpoint *cp,
const string §ion);
};
@@ -259,9 +261,10 @@
void
-LinkDelayEvent::unserialize(Checkpoint *cp, const string §ion)
+LinkDelayEvent::unserialize(Checkpoint *cp, const string §ion,
+ EventQueue *eventq)
{
- Event::unserialize(cp, section);
+ Event::unserialize(cp, section, eventq);
EtherLink *parent;
bool number;
diff -r b2bfc23f932c -r 2cce74fe359e src/dev/x86/Pc.py
--- a/src/dev/x86/Pc.py Fri Nov 15 13:21:15 2013 -0500
+++ b/src/dev/x86/Pc.py Mon Nov 25 11:21:00 2013 -0600
@@ -57,10 +57,9 @@
behind_pci = IsaFake(pio_addr=x86IOAddress(0xcf8), pio_size=8)
# Serial port and terminal
- terminal = Terminal()
com_1 = Uart8250()
com_1.pio_addr = x86IOAddress(0x3f8)
- com_1.terminal = terminal
+ com_1.terminal = Terminal()
# Devices to catch access to non-existant serial ports.
fake_com_2 = IsaFake(pio_addr=x86IOAddress(0x2f8), pio_size=8)
diff -r b2bfc23f932c -r 2cce74fe359e src/python/m5/SimObject.py
--- a/src/python/m5/SimObject.py Fri Nov 15 13:21:15 2013 -0500
+++ b/src/python/m5/SimObject.py Mon Nov 25 11:21:00 2013 -0600
@@ -11,7 +11,8 @@
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2004-2006 The Regents of The University of Michigan
-# Copyright (c) 2010 Advanced Micro Devices, Inc.
+# Copyright (c) 2010-20013 Advanced Micro Devices, Inc.
+# Copyright (c) 2013 Mark D. Hill and David A. Wood
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -528,8 +529,6 @@
#endif
#include <string>
-
-class EventQueue;
''')
for param in params:
param.cxx_predecls(code)
@@ -558,16 +557,11 @@
code.indent()
if cls == SimObject:
code('''
- SimObjectParams()
- {
- extern EventQueue mainEventQueue;
- eventq = &mainEventQueue;
- }
+ SimObjectParams() {}
virtual ~SimObjectParams() {}
std::string name;
PyObject *pyobj;
- EventQueue *eventq;
''')
for param in params:
param.cxx_decl(code)
@@ -582,6 +576,14 @@
return code
+# This *temporary* definition is required to support calls from the
+# SimObject class definition to the MetaSimObject methods (in
+# particular _set_param, which gets called for parameters with default
+# values defined on the SimObject class itself). It will get
+# overridden by the permanent definition (which requires that
+# SimObject be defined) lower in this file.
+def isSimObjectOrVector(value):
+ return False
# The SimObject class is the root of the special hierarchy. Most of
# the code in this class deals with the configuration hierarchy itself
@@ -592,9 +594,10 @@
__metaclass__ = MetaSimObject
type = 'SimObject'
abstract = True
+
cxx_header = "sim/sim_object.hh"
-
cxx_bases = [ "Drainable", "Serializable" ]
+ eventq_index = Param.UInt32(Parent.eventq_index, "Event Queue Index")
@classmethod
def export_method_swig_predecls(cls, code):
diff -r b2bfc23f932c -r 2cce74fe359e src/python/m5/event.py
--- a/src/python/m5/event.py Fri Nov 15 13:21:15 2013 -0500
+++ b/src/python/m5/event.py Mon Nov 25 11:21:00 2013 -0600
@@ -1,4 +1,6 @@
# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2013 Advanced Micro Devices, Inc.
+# Copyright (c) 2013 Mark D. Hill and David A. Wood
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -29,9 +31,9 @@
import m5
import internal.event
-from internal.event import PythonEvent, SimLoopExitEvent as SimExit
+from internal.event import PythonEvent, GlobalSimLoopExitEvent as SimExit
-mainq = internal.event.cvar.mainEventQueue
+mainq = None
def create(obj, priority=None):
if priority is None:
@@ -58,4 +60,10 @@
print "Progress! Time now %fs" % (m5.curTick()/1e12)
self.eventq.schedule(self, m5.curTick() + self.period)
+def getEventQueue(index):
+ return internal.event.getEventQueue(index)
+
+def setEventQueue(eventq):
+ internal.event.curEventQueue(eventq)
+
__all__ = [ 'create', 'Event', 'ProgressEvent', 'SimExit', 'mainq' ]
diff -r b2bfc23f932c -r 2cce74fe359e src/python/m5/main.py
--- a/src/python/m5/main.py Fri Nov 15 13:21:15 2013 -0500
+++ b/src/python/m5/main.py Mon Nov 25 11:21:00 2013 -0600
@@ -190,6 +190,10 @@
fatal("Tracing is not enabled. Compile with TRACING_ON")
+ # Set the main event queue for the main thread.
+ event.mainq = event.getEventQueue(0)
+ event.setEventQueue(event.mainq)
+
if not os.path.isdir(options.outdir):
os.makedirs(options.outdir)
diff -r b2bfc23f932c -r 2cce74fe359e src/python/m5/simulate.py
--- a/src/python/m5/simulate.py Fri Nov 15 13:21:15 2013 -0500
+++ b/src/python/m5/simulate.py Mon Nov 25 11:21:00 2013 -0600
@@ -147,6 +147,13 @@
for obj in root.descendants(): obj.startup()
need_startup = False
+ # Python exit handlers happen in reverse order.
+ # We want to dump stats last.
+ atexit.register(stats.dump)
+
+ # register our C++ exit callback function with Python
+ atexit.register(internal.core.doExitCleanup)
+
for root in need_resume:
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