changeset 0b2e590c85be in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=0b2e590c85be
description:
stats: updates due to changes to ticksToCycles()
diffstat:
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
| 250 +-
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
| 3760 ++++----
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
| 194 +-
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
| 2074 ++--
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
| 204 +-
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
| 2603 +++---
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
| 165 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
| 2773 +++---
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
| 216 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
| 4110 +++++----
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
| 158 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
| 2747 +++---
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
| 172 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
| 3004 +++---
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
| 211 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
| 3642 ++++----
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
| 121 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
| 2283 ++--
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
| 225 +-
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
| 2488 +++---
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
| 235 +-
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
| 2956 +++---
tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
| 79 +-
tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
| 1325 +-
tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
| 80 +-
tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
| 186 +-
tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
| 79 +-
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
| 1492 +-
tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
| 80 +-
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
| 1568 +-
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
| 75 +-
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
| 244 +-
tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
| 77 +-
tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
| 1140 +-
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
| 75 +-
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
| 276 +-
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
| 77 +-
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
| 1494 +-
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
| 30 +-
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
| 96 +-
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
| 75 +-
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
| 1537 +-
tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
| 77 +-
tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
| 1698 ++--
tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
| 30 +-
tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
| 436 +-
tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
| 75 +-
tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
| 1564 +-
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
| 77 +-
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
| 1521 +-
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
| 30 +-
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
| 210 +-
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
| 75 +-
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
| 410 +-
tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
| 77 +-
tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
| 390 +-
tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
| 78 +-
tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
| 370 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
| 182 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
| 16 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
| 172 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
| 16 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
| 158 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
| 2436 ++--
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
| 148 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
| 22 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
| 136 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
| 16 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
| 124 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
| 2799 +++---
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
| 112 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
| 1489 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
| 145 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
| 46 +-
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
| 203 +-
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
| 16 +-
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
| 75 +-
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
| 46 +-
tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
| 75 +-
tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
| 112 +-
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
| 79 +-
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
| 292 +-
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
| 243 +-
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
| 742 +-
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
| 54 +-
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
| 370 +-
86 files changed, 33402 insertions(+), 28716 deletions(-)
diffs (truncated from 95324 to 300 lines):
diff -r 7efa5d115a4e -r 0b2e590c85be
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
Tue Nov 26 17:05:22 2013 -0600
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
Tue Nov 26 17:05:25 2013 -0600
@@ -1,7 +1,9 @@
[root]
type=Root
children=system
+eventq_index=0
full_system=true
+sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -13,15 +15,16 @@
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
-console=/dist/m5/system/binaries/console
+console=/scratch/nilay/GEM5/system/binaries/console
+eventq_index=0
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=tests/halt.sh
symbolfile=
system_rev=1024
@@ -39,6 +42,7 @@
type=Bridge
clk_domain=system.clk_domain
delay=50000
+eventq_index=0
ranges=8796093022208:18446744073709551615
req_size=16
resp_size=16
@@ -48,6 +52,7 @@
[system.clk_domain]
type=SrcClockDomain
clock=1000
+eventq_index=0
voltage_domain=system.voltage_domain
[system.cpu0]
@@ -79,6 +84,8 @@
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu0.dtb
+eventq_index=0
+fetchBufferSize=64
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -143,6 +150,7 @@
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
+eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
@@ -158,6 +166,7 @@
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -180,26 +189,31 @@
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
+eventq_index=0
hit_latency=2
size=32768
[system.cpu0.dtb]
type=AlphaTLB
+eventq_index=0
size=64
[system.cpu0.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
FUList8
FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1
system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3
system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5
system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
+eventq_index=0
[system.cpu0.fuPool.FUList0]
type=FUDesc
children=opList
count=6
+eventq_index=0
opList=system.cpu0.fuPool.FUList0.opList
[system.cpu0.fuPool.FUList0.opList]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=IntAlu
opLat=1
@@ -208,16 +222,19 @@
type=FUDesc
children=opList0 opList1
count=2
+eventq_index=0
opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
[system.cpu0.fuPool.FUList1.opList0]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=IntMult
opLat=3
[system.cpu0.fuPool.FUList1.opList1]
type=OpDesc
+eventq_index=0
issueLat=19
opClass=IntDiv
opLat=20
@@ -226,22 +243,26 @@
type=FUDesc
children=opList0 opList1 opList2
count=4
+eventq_index=0
opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1
system.cpu0.fuPool.FUList2.opList2
[system.cpu0.fuPool.FUList2.opList0]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu0.fuPool.FUList2.opList1]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu0.fuPool.FUList2.opList2]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=FloatCvt
opLat=2
@@ -250,22 +271,26 @@
type=FUDesc
children=opList0 opList1 opList2
count=2
+eventq_index=0
opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1
system.cpu0.fuPool.FUList3.opList2
[system.cpu0.fuPool.FUList3.opList0]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu0.fuPool.FUList3.opList1]
type=OpDesc
+eventq_index=0
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu0.fuPool.FUList3.opList2]
type=OpDesc
+eventq_index=0
issueLat=24
opClass=FloatSqrt
opLat=24
@@ -274,10 +299,12 @@
type=FUDesc
children=opList
count=0
+eventq_index=0
opList=system.cpu0.fuPool.FUList4.opList
[system.cpu0.fuPool.FUList4.opList]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
@@ -286,124 +313,145 @@
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06
opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14
opList15 opList16 opList17 opList18 opList19
count=4
+eventq_index=0
opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01
system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03
system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05
system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07
system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09
system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11
system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13
system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15
system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17
system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19
[system.cpu0.fuPool.FUList5.opList00]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu0.fuPool.FUList5.opList01]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu0.fuPool.FUList5.opList02]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu0.fuPool.FUList5.opList03]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu0.fuPool.FUList5.opList04]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu0.fuPool.FUList5.opList05]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu0.fuPool.FUList5.opList06]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu0.fuPool.FUList5.opList07]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu0.fuPool.FUList5.opList08]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu0.fuPool.FUList5.opList09]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu0.fuPool.FUList5.opList10]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu0.fuPool.FUList5.opList11]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu0.fuPool.FUList5.opList12]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu0.fuPool.FUList5.opList13]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu0.fuPool.FUList5.opList14]
type=OpDesc
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
