> On Dec. 15, 2013, 10:59 p.m., Anthony Gutierrez wrote:
> > src/cpu/simple/atomic.cc, line 403
> > <http://reviews.gem5.org/r/2107/diff/1/?file=38213#file38213line403>
> >
> > memset?
>
> Ali Saidi wrote:
> It's static so mem-setting won't really work (or at least it would have
> to be initialized else where. My goal was simply to create a reusable block
> of all zeros. I'd imagine the compiler will allocate it out of the bas (but
> I'm not sure) so it will be part of a larger memset of that whole area by the
> loader.
>
>
> Anthony Gutierrez wrote:
> Ah. Didn't catch the static part before.
Actually, Mitch just pointed to toward a stack overflow article that it can be
replaced with:
static uint8_t zero_array[64] = {}; and the compile will take care of the rest.
Consider it done.
Thanks,
Ali
- Ali
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
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On Nov. 30, 2013, 11:51 p.m., Ali Saidi wrote:
>
> -----------------------------------------------------------
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/2107/
> -----------------------------------------------------------
>
> (Updated Nov. 30, 2013, 11:51 p.m.)
>
>
> Review request for Default.
>
>
> Repository: gem5
>
>
> Description
> -------
>
> Changeset 10007:7b245b85f5c3
> ---------------------------
> cpu: Add support for instructions that zero cache lines.
>
>
> Diffs
> -----
>
> src/cpu/base_dyn_inst_impl.hh 81d7551dd3be
> src/cpu/o3/lsq_unit.hh 81d7551dd3be
> src/cpu/o3/lsq_unit_impl.hh 81d7551dd3be
> src/cpu/simple/atomic.cc 81d7551dd3be
> src/cpu/simple/timing.cc 81d7551dd3be
> src/mem/request.hh 81d7551dd3be
>
> Diff: http://reviews.gem5.org/r/2107/diff/
>
>
> Testing
> -------
>
>
> Thanks,
>
> Ali Saidi
>
>
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