changeset 552db6109dd3 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=552db6109dd3
description:
ruby: mesi three level: rename incorrectly named files
Two files had been incorrectly named with a .cache suffix.
diffstat:
src/mem/protocol/MESI_Three_Level-L0.cache | 700 -----------------
src/mem/protocol/MESI_Three_Level-L0cache.sm | 700 +++++++++++++++++
src/mem/protocol/MESI_Three_Level-L1.cache | 1046 --------------------------
src/mem/protocol/MESI_Three_Level-L1cache.sm | 1046 ++++++++++++++++++++++++++
src/mem/protocol/MESI_Three_Level.slicc | 4 +-
5 files changed, 1748 insertions(+), 1748 deletions(-)
diffs (truncated from 3522 to 300 lines):
diff -r f81d94b53661 -r 552db6109dd3 src/mem/protocol/MESI_Three_Level-L0.cache
--- a/src/mem/protocol/MESI_Three_Level-L0.cache Thu Feb 20 17:27:07
2014 -0600
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,700 +0,0 @@
-/*
- * Copyright (c) 2013 Mark D. Hill and David A. Wood
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-machine(L0Cache, "MESI Directory L0 Cache")
- : Sequencer * sequencer,
- CacheMemory * Icache,
- CacheMemory * Dcache,
- Cycles request_latency = 2,
- Cycles response_latency = 2,
- bool send_evictions,
-{
- // NODE L0 CACHE
- // From this node's L0 cache to the network
- MessageBuffer bufferFromCache, network="To", physical_network="0",
ordered="true";
-
- // To this node's L0 cache FROM the network
- MessageBuffer bufferToCache, network="From", physical_network="0",
ordered="true";
-
- // Message queue between this controller and the processor
- MessageBuffer mandatoryQueue, ordered="false";
-
- // STATES
- state_declaration(State, desc="Cache states", default="L0Cache_State_I") {
- // Base states
-
- // The cache entry has not been allocated.
- NP, AccessPermission:Invalid, desc="Not present in either cache";
-
- // The cache entry has been allocated, but is not in use.
- I, AccessPermission:Invalid;
-
- // The cache entry is in shared mode. The processor can read this entry
- // but it cannot write to it.
- S, AccessPermission:Read_Only;
-
- // The cache entry is in exclusive mode. The processor can read this
- // entry. It can write to this entry without informing the directory.
- // On writing, the entry moves to M state.
- E, AccessPermission:Read_Only;
-
- // The processor has read and write permissions on this entry.
- M, AccessPermission:Read_Write;
-
- // Transient States
-
- // The cache controller has requested that this entry be fetched in
- // shared state so that the processor can read it.
- IS, AccessPermission:Busy;
-
- // The cache controller has requested that this entry be fetched in
- // modify state so that the processor can read/write it.
- IM, AccessPermission:Busy;
-
- // The cache controller had read permission over the entry. But now the
- // processor needs to write to it. So, the controller has requested for
- // write permission.
- SM, AccessPermission:Read_Only;
- }
-
- // EVENTS
- enumeration(Event, desc="Cache events") {
- // L0 events
- Load, desc="Load request from the home processor";
- Ifetch, desc="I-fetch request from the home processor";
- Store, desc="Store request from the home processor";
-
- Inv, desc="Invalidate request from L2 bank";
-
- // internal generated request
- L0_Replacement, desc="L0 Replacement", format="!r";
-
- // other requests
- Fwd_GETX, desc="GETX from other processor";
- Fwd_GETS, desc="GETS from other processor";
- Fwd_GET_INSTR, desc="GET_INSTR from other processor";
-
- Data, desc="Data for processor";
- Data_Exclusive, desc="Data for processor";
- Data_Stale, desc="Data for processor, but not for storage";
-
- Ack, desc="Ack for processor";
- Ack_all, desc="Last ack for processor";
-
- WB_Ack, desc="Ack for replacement";
- }
-
- // TYPES
-
- // CacheEntry
- structure(Entry, desc="...", interface="AbstractCacheEntry" ) {
- State CacheState, desc="cache state";
- DataBlock DataBlk, desc="data for the block";
- bool Dirty, default="false", desc="data is dirty";
- }
-
- // TBE fields
- structure(TBE, desc="...") {
- Address Addr, desc="Physical address for this TBE";
- State TBEState, desc="Transient state";
- DataBlock DataBlk, desc="Buffer for the data block";
- bool Dirty, default="false", desc="data is dirty";
- int pendingAcks, default="0", desc="number of pending acks";
- }
-
- structure(TBETable, external="yes") {
- TBE lookup(Address);
- void allocate(Address);
- void deallocate(Address);
- bool isPresent(Address);
- }
-
- TBETable TBEs, template="<L0Cache_TBE>", constructor="m_number_of_TBEs";
-
- void set_cache_entry(AbstractCacheEntry a);
- void unset_cache_entry();
- void set_tbe(TBE a);
- void unset_tbe();
- void wakeUpBuffers(Address a);
- void wakeUpAllBuffers(Address a);
- void profileMsgDelay(int virtualNetworkType, Cycles c);
-
- // inclusive cache returns L0 entries only
- Entry getCacheEntry(Address addr), return_by_pointer="yes" {
- Entry Dcache_entry := static_cast(Entry, "pointer", Dcache[addr]);
- if(is_valid(Dcache_entry)) {
- return Dcache_entry;
- }
-
- Entry Icache_entry := static_cast(Entry, "pointer", Icache[addr]);
- return Icache_entry;
- }
-
- Entry getDCacheEntry(Address addr), return_by_pointer="yes" {
- Entry Dcache_entry := static_cast(Entry, "pointer", Dcache[addr]);
- return Dcache_entry;
- }
-
- Entry getICacheEntry(Address addr), return_by_pointer="yes" {
- Entry Icache_entry := static_cast(Entry, "pointer", Icache[addr]);
- return Icache_entry;
- }
-
- State getState(TBE tbe, Entry cache_entry, Address addr) {
- assert((Dcache.isTagPresent(addr) && Icache.isTagPresent(addr)) == false);
-
- if(is_valid(tbe)) {
- return tbe.TBEState;
- } else if (is_valid(cache_entry)) {
- return cache_entry.CacheState;
- }
- return State:NP;
- }
-
- void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
- assert((Dcache.isTagPresent(addr) && Icache.isTagPresent(addr)) == false);
-
- // MUST CHANGE
- if(is_valid(tbe)) {
- tbe.TBEState := state;
- }
-
- if (is_valid(cache_entry)) {
- cache_entry.CacheState := state;
- }
- }
-
- AccessPermission getAccessPermission(Address addr) {
- TBE tbe := TBEs[addr];
- if(is_valid(tbe)) {
- DPRINTF(RubySlicc, "%s\n", L0Cache_State_to_permission(tbe.TBEState));
- return L0Cache_State_to_permission(tbe.TBEState);
- }
-
- Entry cache_entry := getCacheEntry(addr);
- if(is_valid(cache_entry)) {
- DPRINTF(RubySlicc, "%s\n",
L0Cache_State_to_permission(cache_entry.CacheState));
- return L0Cache_State_to_permission(cache_entry.CacheState);
- }
-
- DPRINTF(RubySlicc, "%s\n", AccessPermission:NotPresent);
- return AccessPermission:NotPresent;
- }
-
- DataBlock getDataBlock(Address addr), return_by_ref="yes" {
- TBE tbe := TBEs[addr];
- if(is_valid(tbe)) {
- return tbe.DataBlk;
- }
-
- return getCacheEntry(addr).DataBlk;
- }
-
- void setAccessPermission(Entry cache_entry, Address addr, State state) {
- if (is_valid(cache_entry)) {
- cache_entry.changePermission(L0Cache_State_to_permission(state));
- }
- }
-
- Event mandatory_request_type_to_event(RubyRequestType type) {
- if (type == RubyRequestType:LD) {
- return Event:Load;
- } else if (type == RubyRequestType:IFETCH) {
- return Event:Ifetch;
- } else if ((type == RubyRequestType:ST) || (type ==
RubyRequestType:ATOMIC)) {
- return Event:Store;
- } else {
- error("Invalid RubyRequestType");
- }
- }
-
- int getPendingAcks(TBE tbe) {
- return tbe.pendingAcks;
- }
-
- out_port(requestNetwork_out, CoherenceMsg, bufferFromCache);
-
- // Messages for this L0 cache from the L1 cache
- in_port(messgeBuffer_in, CoherenceMsg, bufferToCache, rank = 1) {
- if (messgeBuffer_in.isReady()) {
- peek(messgeBuffer_in, CoherenceMsg, block_on="Addr") {
- assert(in_msg.Destination == machineID);
-
- Entry cache_entry := getCacheEntry(in_msg.Addr);
- TBE tbe := TBEs[in_msg.Addr];
-
- if(in_msg.Class == CoherenceClass:DATA_EXCLUSIVE) {
- trigger(Event:Data_Exclusive, in_msg.Addr, cache_entry, tbe);
- } else if(in_msg.Class == CoherenceClass:DATA) {
- trigger(Event:Data, in_msg.Addr, cache_entry, tbe);
- } else if(in_msg.Class == CoherenceClass:STALE_DATA) {
- trigger(Event:Data_Stale, in_msg.Addr, cache_entry, tbe);
- } else if (in_msg.Class == CoherenceClass:ACK) {
- trigger(Event:Ack, in_msg.Addr, cache_entry, tbe);
- } else if (in_msg.Class == CoherenceClass:WB_ACK) {
- trigger(Event:WB_Ack, in_msg.Addr, cache_entry, tbe);
- } else if (in_msg.Class == CoherenceClass:INV) {
- trigger(Event:Inv, in_msg.Addr, cache_entry, tbe);
- } else if (in_msg.Class == CoherenceClass:GETX ||
- in_msg.Class == CoherenceClass:UPGRADE) {
- // upgrade transforms to GETX due to race
- trigger(Event:Fwd_GETX, in_msg.Addr, cache_entry, tbe);
- } else if (in_msg.Class == CoherenceClass:GETS) {
- trigger(Event:Fwd_GETS, in_msg.Addr, cache_entry, tbe);
- } else if (in_msg.Class == CoherenceClass:GET_INSTR) {
- trigger(Event:Fwd_GET_INSTR, in_msg.Addr, cache_entry, tbe);
- } else {
- error("Invalid forwarded request type");
- }
- }
- }
- }
-
- // Mandatory Queue betweens Node's CPU and it's L0 caches
- in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...", rank =
0) {
- if (mandatoryQueue_in.isReady()) {
- peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
-
- // Check for data access to blocks in I-cache and ifetchs to blocks in
D-cache
-
- if (in_msg.Type == RubyRequestType:IFETCH) {
- // ** INSTRUCTION ACCESS ***
-
- Entry Icache_entry := getICacheEntry(in_msg.LineAddress);
- if (is_valid(Icache_entry)) {
- // The tag matches for the L0, so the L0 asks the L2 for it.
- trigger(mandatory_request_type_to_event(in_msg.Type),
in_msg.LineAddress,
- Icache_entry, TBEs[in_msg.LineAddress]);
- } else {
-
- // Check to see if it is in the OTHER L0
- Entry Dcache_entry := getDCacheEntry(in_msg.LineAddress);
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