changeset 5e1f04b4d5e4 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=5e1f04b4d5e4
description:
config: remove ruby_fs.py
The patch removes the ruby_fs.py file. The functionality is being
moved to
fs.py. This would being ruby fs simulations in line with how ruby se
simulations are started (using --ruby option). The alpha fs config
functions
are being combined for classing and ruby memory systems. This required
renaming the piobus in ruby to iobus. So, we will have stats being
renamed
in the stats file for ruby fs regression.
diffstat:
configs/common/FSConfig.py | 99 +++++++--------------
configs/example/fs.py | 102 +++++++++++++++++-----
configs/example/ruby_fs.py | 146 ---------------------------------
configs/example/se.py | 4 +-
configs/ruby/Ruby.py | 3 +
tests/configs/pc-simple-timing-ruby.py | 4 +-
6 files changed, 120 insertions(+), 238 deletions(-)
diffs (truncated from 502 to 300 lines):
diff -r 37e333de580f -r 5e1f04b4d5e4 configs/common/FSConfig.py
--- a/configs/common/FSConfig.py Thu Mar 20 08:03:09 2014 -0500
+++ b/configs/common/FSConfig.py Thu Mar 20 08:03:09 2014 -0500
@@ -55,8 +55,8 @@
default = Self.badaddr_responder.pio
-def makeLinuxAlphaSystem(mem_mode, mdesc = None):
- IO_address_space_base = 0x80000000000
+def makeLinuxAlphaSystem(mem_mode, mdesc = None, ruby = False):
+
class BaseTsunami(Tsunami):
ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
ide = IdeController(disks=[Parent.disk0, Parent.disk2],
@@ -67,73 +67,44 @@
# generic system
mdesc = SysConfig()
self.readfile = mdesc.script()
+
+ self.tsunami = BaseTsunami()
+
+ # Create the io bus to connect all device ports
self.iobus = NoncoherentBus()
- self.membus = MemBus()
- # By default the bridge responds to all addresses above the I/O
- # base address (including the PCI config space)
- self.bridge = Bridge(delay='50ns',
+ self.tsunami.attachIO(self.iobus)
+
+ self.tsunami.ide.pio = self.iobus.master
+ self.tsunami.ide.config = self.iobus.master
+
+ self.tsunami.ethernet.pio = self.iobus.master
+ self.tsunami.ethernet.config = self.iobus.master
+
+ if ruby:
+ # Store the dma devices for later connection to dma ruby ports.
+ # Append an underscore to dma_ports to avoid the SimObjectVector check.
+ self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
+ else:
+ self.membus = MemBus()
+
+ # By default the bridge responds to all addresses above the I/O
+ # base address (including the PCI config space)
+ IO_address_space_base = 0x80000000000
+ self.bridge = Bridge(delay='50ns',
ranges = [AddrRange(IO_address_space_base, Addr.max)])
+ self.bridge.master = self.iobus.slave
+ self.bridge.slave = self.membus.master
+
+ self.tsunami.ide.dma = self.iobus.slave
+ self.tsunami.ethernet.dma = self.iobus.slave
+
+ self.system_port = self.membus.slave
+
self.mem_ranges = [AddrRange(mdesc.mem())]
- self.bridge.master = self.iobus.slave
- self.bridge.slave = self.membus.master
self.disk0 = CowIdeDisk(driveID='master')
self.disk2 = CowIdeDisk(driveID='master')
self.disk0.childImage(mdesc.disk())
self.disk2.childImage(disk('linux-bigswap2.img'))
- self.tsunami = BaseTsunami()
- self.tsunami.attachIO(self.iobus)
- self.tsunami.ide.pio = self.iobus.master
- self.tsunami.ide.config = self.iobus.master
- self.tsunami.ide.dma = self.iobus.slave
- self.tsunami.ethernet.pio = self.iobus.master
- self.tsunami.ethernet.config = self.iobus.master
- self.tsunami.ethernet.dma = self.iobus.slave
- self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
- read_only = True))
- self.intrctrl = IntrControl()
- self.mem_mode = mem_mode
- self.terminal = Terminal()
- self.kernel = binary('vmlinux')
- self.pal = binary('ts_osfpal')
- self.console = binary('console')
- self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
-
- self.system_port = self.membus.slave
-
- return self
-
-def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
- class BaseTsunami(Tsunami):
- ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
- ide = IdeController(disks=[Parent.disk0, Parent.disk2],
- pci_func=0, pci_dev=0, pci_bus=0)
- self = LinuxAlphaSystem()
- self.mem_ranges = [AddrRange(mdesc.mem())]
- if not mdesc:
- # generic system
- mdesc = SysConfig()
- self.readfile = mdesc.script()
-
- # Create pio bus to connect all device pio ports to rubymem's pio port
- self.piobus = NoncoherentBus()
-
- self.disk0 = CowIdeDisk(driveID='master')
- self.disk2 = CowIdeDisk(driveID='master')
- self.disk0.childImage(mdesc.disk())
- self.disk2.childImage(disk('linux-bigswap2.img'))
- self.tsunami = BaseTsunami()
- self.tsunami.attachIO(self.piobus)
- self.tsunami.ide.pio = self.piobus.master
- self.tsunami.ide.config = self.piobus.master
- self.tsunami.ethernet.pio = self.piobus.master
- self.tsunami.ethernet.config = self.piobus.master
-
- #
- # Store the dma devices for later connection to dma ruby ports.
- # Append an underscore to dma_devices to avoid the SimObjectVector check.
- #
- self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
-
self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
read_only = True))
self.intrctrl = IntrControl()
@@ -392,12 +363,12 @@
def connectX86RubySystem(x86_sys):
# North Bridge
- x86_sys.piobus = NoncoherentBus()
+ x86_sys.iobus = NoncoherentBus()
# add the ide to the list of dma devices that later need to attach to
# dma controllers
x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
- x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports)
+ x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports)
def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None,
diff -r 37e333de580f -r 5e1f04b4d5e4 configs/example/fs.py
--- a/configs/example/fs.py Thu Mar 20 08:03:09 2014 -0500
+++ b/configs/example/fs.py Thu Mar 20 08:03:09 2014 -0500
@@ -10,6 +10,8 @@
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
+# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
+# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
@@ -37,6 +39,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Ali Saidi
+# Brad Beckmann
import optparse
import sys
@@ -47,6 +50,9 @@
from m5.util import addToPath, fatal
addToPath('../common')
+addToPath('../ruby')
+
+import Ruby
from FSConfig import *
from SysPaths import *
@@ -61,6 +67,10 @@
Options.addCommonOptions(parser)
Options.addFSOptions(parser)
+# Add the ruby specific and protocol specific options
+if '--ruby' in sys.argv:
+ Ruby.define_options(parser)
+
(options, args) = parser.parse_args()
if args:
@@ -104,13 +114,14 @@
np = options.num_cpus
if buildEnv['TARGET_ISA'] == "alpha":
- test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
+ test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby)
elif buildEnv['TARGET_ISA'] == "mips":
test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
elif buildEnv['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0])
elif buildEnv['TARGET_ISA'] == "x86":
- test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0])
+ test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
+ options.ruby)
elif buildEnv['TARGET_ISA'] == "arm":
test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
options.dtb_filename,
@@ -120,6 +131,9 @@
else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
+# Set the cache line size for the entire system
+test_sys.cache_line_size = options.cacheline_size
+
# Create a top-level voltage domain
test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
@@ -156,32 +170,72 @@
if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
test_sys.vm = KvmVM()
-if options.caches or options.l2cache:
- # By default the IOCache runs at the system clock
- test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
- test_sys.iocache.cpu_side = test_sys.iobus.master
- test_sys.iocache.mem_side = test_sys.membus.slave
+if options.ruby:
+ # Check for timing mode because ruby does not support atomic accesses
+ if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
+ print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
+ sys.exit(1)
+
+ Ruby.create_system(options, test_sys, test_sys.iobus, test_sys._dma_ports)
+
+ # Create a seperate clock domain for Ruby
+ test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
+ voltage_domain = test_sys.voltage_domain)
+
+ for (i, cpu) in enumerate(test_sys.cpu):
+ #
+ # Tie the cpu ports to the correct ruby system ports
+ #
+ cpu.clk_domain = test_sys.cpu_clk_domain
+ cpu.createThreads()
+ cpu.createInterruptController()
+
+ cpu.icache_port = test_sys.ruby._cpu_ruby_ports[i].slave
+ cpu.dcache_port = test_sys.ruby._cpu_ruby_ports[i].slave
+
+ if buildEnv['TARGET_ISA'] == "x86":
+ cpu.itb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave
+ cpu.dtb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave
+
+ cpu.interrupts.pio = test_sys.ruby._cpu_ruby_ports[i].master
+ cpu.interrupts.int_master = test_sys.ruby._cpu_ruby_ports[i].slave
+ cpu.interrupts.int_slave = test_sys.ruby._cpu_ruby_ports[i].master
+
+ test_sys.ruby._cpu_ruby_ports[i].access_phys_mem = True
+
+ # Create the appropriate memory controllers and connect them to the
+ # PIO bus
+ test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges]
+ for i in xrange(len(test_sys.mem_ctrls)):
+ test_sys.mem_ctrls[i].port = test_sys.iobus.master
+
else:
- test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
- test_sys.iobridge.slave = test_sys.iobus.master
- test_sys.iobridge.master = test_sys.membus.slave
+ if options.caches or options.l2cache:
+ # By default the IOCache runs at the system clock
+ test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
+ test_sys.iocache.cpu_side = test_sys.iobus.master
+ test_sys.iocache.mem_side = test_sys.membus.slave
+ else:
+ test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
+ test_sys.iobridge.slave = test_sys.iobus.master
+ test_sys.iobridge.master = test_sys.membus.slave
-# Sanity check
-if options.fastmem:
- if TestCPUClass != AtomicSimpleCPU:
- fatal("Fastmem can only be used with atomic CPU!")
- if (options.caches or options.l2cache):
- fatal("You cannot use fastmem in combination with caches!")
+ # Sanity check
+ if options.fastmem:
+ if TestCPUClass != AtomicSimpleCPU:
+ fatal("Fastmem can only be used with atomic CPU!")
+ if (options.caches or options.l2cache):
+ fatal("You cannot use fastmem in combination with caches!")
-for i in xrange(np):
- if options.fastmem:
- test_sys.cpu[i].fastmem = True
- if options.checker:
- test_sys.cpu[i].addCheckerCpu()
- test_sys.cpu[i].createThreads()
+ for i in xrange(np):
+ if options.fastmem:
+ test_sys.cpu[i].fastmem = True
+ if options.checker:
+ test_sys.cpu[i].addCheckerCpu()
+ test_sys.cpu[i].createThreads()
-CacheConfig.config_cache(options, test_sys)
-MemConfig.config_mem(options, test_sys)
+ CacheConfig.config_cache(options, test_sys)
+ MemConfig.config_mem(options, test_sys)
if len(bm) == 2:
if buildEnv['TARGET_ISA'] == 'alpha':
diff -r 37e333de580f -r 5e1f04b4d5e4 configs/example/ruby_fs.py
--- a/configs/example/ruby_fs.py Thu Mar 20 08:03:09 2014 -0500
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
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