I have a newby question. I would like to modify the Interconnect module(s) located between the CPU and Slave module to remap the Slave module address space. The diagram showing these modules can be seen in the ARM gem5 Tutorial, Bischoff & Hansson, slide 70, titled Ports, Masters, and Slaves.
I appears there a couple of paths. The first is to modify the AddrMapper class the second is to modify or write a Ruby script. It seems there are some issues with Ruby and ARM non-contiguous memory. Any suggestions on a place to start and route to take? Thanks, Roger -- _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
