changeset bbfa3152bdea in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=bbfa3152bdea description: arch: remove inline specifiers on all inst constrs, all ISAs
With (upcoming) separate compilation, they are useless. Only link-time optimization could re-inline them, but ideally feedback-directed optimization would choose to do so only for profitable (i.e. common) instructions. diffstat: src/arch/alpha/isa/main.isa | 2 +- src/arch/alpha/isa/mem.isa | 2 +- src/arch/arm/isa/templates/basic.isa | 2 +- src/arch/arm/isa/templates/branch.isa | 12 ++++---- src/arch/arm/isa/templates/branch64.isa | 10 ++++---- src/arch/arm/isa/templates/data64.isa | 20 ++++++++-------- src/arch/arm/isa/templates/mem.isa | 24 +++++++++--------- src/arch/arm/isa/templates/mem64.isa | 2 +- src/arch/arm/isa/templates/misc.isa | 36 ++++++++++++++-------------- src/arch/arm/isa/templates/misc64.isa | 4 +- src/arch/arm/isa/templates/mult.isa | 4 +- src/arch/arm/isa/templates/pred.isa | 6 ++-- src/arch/arm/isa/templates/vfp.isa | 8 +++--- src/arch/arm/isa/templates/vfp64.isa | 10 ++++---- src/arch/mips/isa/formats/basic.isa | 2 +- src/arch/mips/isa/formats/mem.isa | 2 +- src/arch/power/isa/formats/basic.isa | 2 +- src/arch/power/isa/formats/integer.isa | 6 ++-- src/arch/power/isa/formats/mem.isa | 2 +- src/arch/sparc/isa/formats/basic.isa | 4 +- src/arch/sparc/isa/formats/mem/blockmem.isa | 4 +- src/arch/sparc/isa/formats/priv.isa | 2 +- src/arch/x86/isa/formats/basic.isa | 2 +- src/arch/x86/isa/macroop.isa | 2 +- src/arch/x86/isa/microops/fpop.isa | 2 +- src/arch/x86/isa/microops/ldstop.isa | 2 +- src/arch/x86/isa/microops/limmop.isa | 2 +- src/arch/x86/isa/microops/mediaop.isa | 4 +- src/arch/x86/isa/microops/regop.isa | 4 +- src/arch/x86/isa/microops/seqop.isa | 4 +- src/arch/x86/isa/microops/specop.isa | 6 ++-- 31 files changed, 97 insertions(+), 97 deletions(-) diffs (truncated from 966 to 300 lines): diff -r badc31a41a87 -r bbfa3152bdea src/arch/alpha/isa/main.isa --- a/src/arch/alpha/isa/main.isa Fri May 09 18:58:46 2014 -0400 +++ b/src/arch/alpha/isa/main.isa Fri May 09 18:58:46 2014 -0400 @@ -314,7 +314,7 @@ // Basic instruction class constructor template. def template BasicConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst) + %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) { %(constructor)s; diff -r badc31a41a87 -r bbfa3152bdea src/arch/alpha/isa/mem.isa --- a/src/arch/alpha/isa/mem.isa Fri May 09 18:58:46 2014 -0400 +++ b/src/arch/alpha/isa/mem.isa Fri May 09 18:58:46 2014 -0400 @@ -155,7 +155,7 @@ }}; def template LoadStoreConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst) + %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) { %(constructor)s; diff -r badc31a41a87 -r bbfa3152bdea src/arch/arm/isa/templates/basic.isa --- a/src/arch/arm/isa/templates/basic.isa Fri May 09 18:58:46 2014 -0400 +++ b/src/arch/arm/isa/templates/basic.isa Fri May 09 18:58:46 2014 -0400 @@ -73,7 +73,7 @@ }}; def template BasicConstructor64 {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) + %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) { %(constructor)s; } diff -r badc31a41a87 -r bbfa3152bdea src/arch/arm/isa/templates/branch.isa --- a/src/arch/arm/isa/templates/branch.isa Fri May 09 18:58:46 2014 -0400 +++ b/src/arch/arm/isa/templates/branch.isa Fri May 09 18:58:46 2014 -0400 @@ -48,7 +48,7 @@ }}; def template BranchImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, int32_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) { @@ -81,7 +81,7 @@ }}; def template BranchImmCondConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, int32_t _imm, ConditionCode _condCode) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -110,7 +110,7 @@ }}; def template BranchRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1) { @@ -140,7 +140,7 @@ }}; def template BranchRegCondConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1, ConditionCode _condCode) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -187,7 +187,7 @@ }}; def template BranchRegRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2) @@ -218,7 +218,7 @@ // Only used by CBNZ, CBZ which is conditional based on // a register value even though the instruction is always unconditional. def template BranchImmRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, int32_t _imm, IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1) diff -r badc31a41a87 -r bbfa3152bdea src/arch/arm/isa/templates/branch64.isa --- a/src/arch/arm/isa/templates/branch64.isa Fri May 09 18:58:46 2014 -0400 +++ b/src/arch/arm/isa/templates/branch64.isa Fri May 09 18:58:46 2014 -0400 @@ -48,7 +48,7 @@ }}; def template BranchImm64Constructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, int64_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) { @@ -68,7 +68,7 @@ }}; def template BranchImmCond64Constructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, int64_t _imm, ConditionCode _condCode) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -89,7 +89,7 @@ }}; def template BranchReg64Constructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1) { @@ -109,7 +109,7 @@ }}; def template BranchImmReg64Constructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, int64_t _imm, IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1) @@ -130,7 +130,7 @@ }}; def template BranchImmImmReg64Constructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, int64_t _imm1, int64_t _imm2, IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, diff -r badc31a41a87 -r bbfa3152bdea src/arch/arm/isa/templates/data64.isa --- a/src/arch/arm/isa/templates/data64.isa Fri May 09 18:58:46 2014 -0400 +++ b/src/arch/arm/isa/templates/data64.isa Fri May 09 18:58:46 2014 -0400 @@ -49,7 +49,7 @@ }}; def template DataXImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm) @@ -73,7 +73,7 @@ }}; def template DataXSRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, @@ -99,7 +99,7 @@ }}; def template DataXERegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, @@ -124,7 +124,7 @@ }}; def template DataX1RegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1) @@ -145,7 +145,7 @@ }}; def template DataX2RegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) @@ -168,7 +168,7 @@ }}; def template DataX2RegImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, @@ -192,7 +192,7 @@ }}; def template DataX3RegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, @@ -216,7 +216,7 @@ }}; def template DataXCondCompImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint64_t _imm, ConditionCode _condCode, @@ -241,7 +241,7 @@ }}; def template DataXCondCompRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2, ConditionCode _condCode, @@ -266,7 +266,7 @@ }}; def template DataXCondSelConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, diff -r badc31a41a87 -r bbfa3152bdea src/arch/arm/isa/templates/mem.isa --- a/src/arch/arm/isa/templates/mem.isa Fri May 09 18:58:46 2014 -0400 +++ b/src/arch/arm/isa/templates/mem.isa Fri May 09 18:58:46 2014 -0400 @@ -860,7 +860,7 @@ }}; def template RfeConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _base, int _mode, bool _wb) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, (IntRegIndex)_base, (AddrMode)_mode, _wb) @@ -889,7 +889,7 @@ }}; def template SrsConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _regMode, int _mode, bool _wb) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, (OperatingMode)_regMode, (AddrMode)_mode, _wb) @@ -912,7 +912,7 @@ }}; def template SwapConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _op1, uint32_t _base) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base) @@ -927,7 +927,7 @@ }}; def template LoadStoreDImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, int32_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -952,7 +952,7 @@ }}; def template StoreExDImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _result, uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, int32_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -979,7 +979,7 @@ }}; def template LoadStoreImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) @@ -1002,7 +1002,7 @@ }}; def template StoreExImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _result, uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev