changeset c09802451018 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c09802451018
description:
arm: Panics in miscreg read functions can be tripped by O3 model
Unimplemented miscregs for the generic timer were guarded by panics
in arm/isa.cc which can be tripped by the O3 model if it speculatively
executes a wrong path containing a mrs instruction with a bad miscreg
index. These registers were flagged as implemented and accessible.
This patch changes the miscreg info bit vector to flag them as
unimplemented and inaccessible. In this case, and UndefinedInst
fault will be generated if the register access is not trapped
by a hypervisor.
diffstat:
src/arch/arm/isa.cc | 31 +++++++++++++++----------------
src/arch/arm/isa/insts/misc.isa | 4 ++--
src/arch/arm/miscregs.cc | 34 +++++++++++++++++-----------------
3 files changed, 34 insertions(+), 35 deletions(-)
diffs (158 lines):
diff -r 7fef26827810 -r c09802451018 src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc Fri May 09 18:58:46 2014 -0400
+++ b/src/arch/arm/isa.cc Fri May 09 18:58:46 2014 -0400
@@ -729,30 +729,30 @@
return getArchTimer(tc, tc->cpuId())->control();
// PL1 phys. timer, secure
// AArch64
- case MISCREG_CNTPS_CVAL_EL1:
- case MISCREG_CNTPS_TVAL_EL1:
- case MISCREG_CNTPS_CTL_EL1:
+ // case MISCREG_CNTPS_CVAL_EL1:
+ // case MISCREG_CNTPS_TVAL_EL1:
+ // case MISCREG_CNTPS_CTL_EL1:
// PL2 phys. timer, non-secure
// AArch32
- case MISCREG_CNTHCTL:
- case MISCREG_CNTHP_CVAL:
- case MISCREG_CNTHP_TVAL:
- case MISCREG_CNTHP_CTL:
+ // case MISCREG_CNTHCTL:
+ // case MISCREG_CNTHP_CVAL:
+ // case MISCREG_CNTHP_TVAL:
+ // case MISCREG_CNTHP_CTL:
// AArch64
- case MISCREG_CNTHCTL_EL2:
- case MISCREG_CNTHP_CVAL_EL2:
- case MISCREG_CNTHP_TVAL_EL2:
- case MISCREG_CNTHP_CTL_EL2:
+ // case MISCREG_CNTHCTL_EL2:
+ // case MISCREG_CNTHP_CVAL_EL2:
+ // case MISCREG_CNTHP_TVAL_EL2:
+ // case MISCREG_CNTHP_CTL_EL2:
// Virtual timer
// AArch32
- case MISCREG_CNTV_CVAL:
- case MISCREG_CNTV_TVAL:
- case MISCREG_CNTV_CTL:
+ // case MISCREG_CNTV_CVAL:
+ // case MISCREG_CNTV_TVAL:
+ // case MISCREG_CNTV_CTL:
// AArch64
// case MISCREG_CNTV_CVAL_EL2:
// case MISCREG_CNTV_TVAL_EL2:
// case MISCREG_CNTV_CTL_EL2:
- panic("Generic Timer register not implemented\n");
+ default:
break;
}
@@ -1902,7 +1902,6 @@
// case MISCREG_CNTV_CVAL_EL2:
// case MISCREG_CNTV_TVAL_EL2:
// case MISCREG_CNTV_CTL_EL2:
- panic("Generic Timer register not implemented\n");
break;
}
}
diff -r 7fef26827810 -r c09802451018 src/arch/arm/isa/insts/misc.isa
--- a/src/arch/arm/isa/insts/misc.isa Fri May 09 18:58:46 2014 -0400
+++ b/src/arch/arm/isa/insts/misc.isa Fri May 09 18:58:46 2014 -0400
@@ -851,7 +851,7 @@
// if we're in non secure PL1 mode then we can trap regargless of whether
// the register is accessable, in other modes we trap if only if the
register
// IS accessable.
- if (!canRead & !(hypTrap & !inUserMode(Cpsr) & !inSecureState(Scr, Cpsr)))
{
+ if (!canRead && !(hypTrap && !inUserMode(Cpsr) && !inSecureState(Scr,
Cpsr))) {
return new UndefinedInstruction(machInst, false, mnemonic);
}
if (hypTrap) {
@@ -906,7 +906,7 @@
// if we're in non secure PL1 mode then we can trap regargless of whether
// the register is accessable, in other modes we trap if only if the
register
// IS accessable.
- if (!canRead & !(hypTrap & !inUserMode(Cpsr) & !inSecureState(Scr, Cpsr)))
{
+ if (!canRead && !(hypTrap && !inUserMode(Cpsr) && !inSecureState(Scr,
Cpsr))) {
return new UndefinedInstruction(machInst, false, mnemonic);
}
if (hypTrap) {
diff -r 7fef26827810 -r c09802451018 src/arch/arm/miscregs.cc
--- a/src/arch/arm/miscregs.cc Fri May 09 18:58:46 2014 -0400
+++ b/src/arch/arm/miscregs.cc Fri May 09 18:58:46 2014 -0400
@@ -714,15 +714,15 @@
// MISCREG_CNTP_CTL_S
bitset<NUM_MISCREG_INFOS>(string("0011001100111110000")),
// MISCREG_CNTV_TVAL
- bitset<NUM_MISCREG_INFOS>(string("1111111111111100001")),
+ bitset<NUM_MISCREG_INFOS>(string("0111100000000000000")),
// MISCREG_CNTV_CTL
- bitset<NUM_MISCREG_INFOS>(string("1111111111111100001")),
+ bitset<NUM_MISCREG_INFOS>(string("0111100000000000000")),
// MISCREG_CNTHCTL
- bitset<NUM_MISCREG_INFOS>(string("1100110000000000001")),
+ bitset<NUM_MISCREG_INFOS>(string("0100100000000000000")),
// MISCREG_CNTHP_TVAL
- bitset<NUM_MISCREG_INFOS>(string("1100110000000000001")),
+ bitset<NUM_MISCREG_INFOS>(string("0100100000000000000")),
// MISCREG_CNTHP_CTL
- bitset<NUM_MISCREG_INFOS>(string("1100110000000000001")),
+ bitset<NUM_MISCREG_INFOS>(string("0100100000000000000")),
// MISCREG_IL1DATA0
bitset<NUM_MISCREG_INFOS>(string("1111111111000000000")),
// MISCREG_IL1DATA1
@@ -762,11 +762,11 @@
// MISCREG_CNTP_CVAL_S
bitset<NUM_MISCREG_INFOS>(string("0011001100111110000")),
// MISCREG_CNTV_CVAL
- bitset<NUM_MISCREG_INFOS>(string("1111111111111100001")),
+ bitset<NUM_MISCREG_INFOS>(string("0111100000000000000")),
// MISCREG_CNTVOFF
bitset<NUM_MISCREG_INFOS>(string("1100110000000000001")),
// MISCREG_CNTHP_CVAL
- bitset<NUM_MISCREG_INFOS>(string("1100110000000000001")),
+ bitset<NUM_MISCREG_INFOS>(string("0100100000000000000")),
// MISCREG_CPUMERRSR
bitset<NUM_MISCREG_INFOS>(string("1111111111000000000")),
// MISCREG_L2MERRSR
@@ -1258,11 +1258,11 @@
// MISCREG_CNTP_CVAL_EL0
bitset<NUM_MISCREG_INFOS>(string("1111111111111100001")),
// MISCREG_CNTV_TVAL_EL0
- bitset<NUM_MISCREG_INFOS>(string("1111111111111100001")),
+ bitset<NUM_MISCREG_INFOS>(string("0111100000000000000")),
// MISCREG_CNTV_CTL_EL0
- bitset<NUM_MISCREG_INFOS>(string("1111111111111100001")),
+ bitset<NUM_MISCREG_INFOS>(string("0111100000000000000")),
// MISCREG_CNTV_CVAL_EL0
- bitset<NUM_MISCREG_INFOS>(string("1111111111111100001")),
+ bitset<NUM_MISCREG_INFOS>(string("0111100000000000000")),
// MISCREG_PMEVCNTR0_EL0
bitset<NUM_MISCREG_INFOS>(string("1111111111111100001")),
// MISCREG_PMEVCNTR1_EL0
@@ -1290,19 +1290,19 @@
// MISCREG_CNTVOFF_EL2
bitset<NUM_MISCREG_INFOS>(string("1111110000000000001")),
// MISCREG_CNTHCTL_EL2
- bitset<NUM_MISCREG_INFOS>(string("1111110000000000001")),
+ bitset<NUM_MISCREG_INFOS>(string("0111100000000000000")),
// MISCREG_CNTHP_TVAL_EL2
- bitset<NUM_MISCREG_INFOS>(string("1111110000000000001")),
+ bitset<NUM_MISCREG_INFOS>(string("0111100000000000000")),
// MISCREG_CNTHP_CTL_EL2
- bitset<NUM_MISCREG_INFOS>(string("1111110000000000001")),
+ bitset<NUM_MISCREG_INFOS>(string("0111100000000000000")),
// MISCREG_CNTHP_CVAL_EL2
- bitset<NUM_MISCREG_INFOS>(string("1111110000000000001")),
+ bitset<NUM_MISCREG_INFOS>(string("0111100000000000000")),
// MISCREG_CNTPS_TVAL_EL1
- bitset<NUM_MISCREG_INFOS>(string("1111111111111100001")),
+ bitset<NUM_MISCREG_INFOS>(string("0111100000000000000")),
// MISCREG_CNTPS_CTL_EL1
- bitset<NUM_MISCREG_INFOS>(string("1111111111111100001")),
+ bitset<NUM_MISCREG_INFOS>(string("0111100000000000000")),
// MISCREG_CNTPS_CVAL_EL1
- bitset<NUM_MISCREG_INFOS>(string("1111111111111100001")),
+ bitset<NUM_MISCREG_INFOS>(string("0111100000000000000")),
// MISCREG_IL1DATA0_EL1
bitset<NUM_MISCREG_INFOS>(string("1111111111000000001")),
// MISCREG_IL1DATA1_EL1
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