changeset cc6408469397 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=cc6408469397
description:
tests: update eio ref outputs for new stats
Also committed reference config.json files for
the eio tests.
diffstat:
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini | 2 +
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.json | 186 ++
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout | 6 +-
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt | 45 +-
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini | 2 +
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.json | 322 +++
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout | 6 +-
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt | 45 +-
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini | 8 +
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.json | 829
++++++++++
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr | 3 +-
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout | 6 +-
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt | 150 +-
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini | 8 +
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.json | 805
+++++++++
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr | 7 +-
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout | 6 +-
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt | 150 +-
18 files changed, 2552 insertions(+), 34 deletions(-)
diffs (truncated from 2928 to 300 lines):
diff -r 9eab5efc02e8 -r cc6408469397
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
Fri May 09 18:58:50 2014 -0400
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
Sat May 10 22:13:51 2014 -0400
@@ -43,6 +43,7 @@
[system.cpu]
type=AtomicSimpleCPU
children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
@@ -70,6 +71,7 @@
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
+socket_id=0
switched_out=false
system=system
tracer=system.cpu.tracer
diff -r 9eab5efc02e8 -r cc6408469397
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.json
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.json
Sat May 10 22:13:51 2014 -0400
@@ -0,0 +1,186 @@
+{
+ "name": null,
+ "sim_quantum": 0,
+ "system": {
+ "membus": {
+ "slave": {
+ "peer": [
+ "system.system_port",
+ "system.cpu.icache_port",
+ "system.cpu.dcache_port"
+ ],
+ "role": "SLAVE"
+ },
+ "name": "membus",
+ "header_cycles": 1,
+ "width": 8,
+ "eventq_index": 0,
+ "master": {
+ "peer": [
+ "system.physmem.port"
+ ],
+ "role": "MASTER"
+ },
+ "cxx_class": "CoherentBus",
+ "path": "system.membus",
+ "type": "CoherentBus",
+ "use_default_range": false
+ },
+ "voltage_domain": {
+ "eventq_index": 0,
+ "path": "system.voltage_domain",
+ "type": "VoltageDomain",
+ "name": "voltage_domain",
+ "cxx_class": "VoltageDomain"
+ },
+ "physmem": {
+ "latency": 3.0000000000000004e-08,
+ "name": "physmem",
+ "eventq_index": 0,
+ "latency_var": 0.0,
+ "conf_table_reported": true,
+ "cxx_class": "SimpleMemory",
+ "path": "system.physmem",
+ "null": false,
+ "type": "SimpleMemory",
+ "port": {
+ "peer": "system.membus.master[0]",
+ "role": "SLAVE"
+ },
+ "in_addr_map": true
+ },
+ "cxx_class": "System",
+ "load_offset": 0,
+ "work_end_ckpt_count": 0,
+ "work_begin_ckpt_count": 0,
+ "clk_domain": {
+ "name": "clk_domain",
+ "clock": 1e-09,
+ "eventq_index": 0,
+ "cxx_class": "SrcClockDomain",
+ "path": "system.clk_domain",
+ "type": "SrcClockDomain"
+ },
+ "eventq_index": 0,
+ "work_end_exit_count": 0,
+ "type": "System",
+ "cache_line_size": 64,
+ "work_cpus_ckpt_count": 0,
+ "work_begin_exit_count": 0,
+ "path": "system",
+ "cpu_clk_domain": {
+ "name": "cpu_clk_domain",
+ "clock": 5e-10,
+ "eventq_index": 0,
+ "cxx_class": "SrcClockDomain",
+ "path": "system.cpu_clk_domain",
+ "type": "SrcClockDomain"
+ },
+ "mem_mode": "atomic",
+ "name": "system",
+ "init_param": 0,
+ "system_port": {
+ "peer": "system.membus.slave[0]",
+ "role": "MASTER"
+ },
+ "load_addr_mask": 1099511627775,
+ "work_item_id": -1,
+ "num_work_ids": 16,
+ "cpu": [
+ {
+ "simpoint_interval": 100000000,
+ "do_statistics_insts": true,
+ "numThreads": 1,
+ "itb": {
+ "name": "itb",
+ "eventq_index": 0,
+ "cxx_class": "AlphaISA::TLB",
+ "path": "system.cpu.itb",
+ "type": "AlphaTLB",
+ "size": 48
+ },
+ "function_trace": false,
+ "do_checkpoint_insts": true,
+ "cxx_class": "AtomicSimpleCPU",
+ "max_loads_all_threads": 0,
+ "simpoint_profile": false,
+ "simulate_data_stalls": false,
+ "function_trace_start": 0,
+ "cpu_id": 0,
+ "width": 1,
+ "eventq_index": 0,
+ "do_quiesce": true,
+ "type": "AtomicSimpleCPU",
+ "fastmem": false,
+ "profile": 0.0,
+ "icache_port": {
+ "peer": "system.membus.slave[1]",
+ "role": "MASTER"
+ },
+ "interrupts": {
+ "eventq_index": 0,
+ "path": "system.cpu.interrupts",
+ "type": "AlphaInterrupts",
+ "name": "interrupts",
+ "cxx_class": "AlphaISA::Interrupts"
+ },
+ "socket_id": 0,
+ "max_insts_all_threads": 0,
+ "path": "system.cpu",
+ "isa": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu.isa",
+ "type": "AlphaISA",
+ "name": "isa",
+ "cxx_class": "AlphaISA::ISA"
+ }
+ ],
+ "switched_out": false,
+ "workload": [
+ {
+ "name": "workload",
+ "eventq_index": 0,
+ "cxx_class": "EioProcess",
+ "path": "system.cpu.workload",
+ "max_stack_size": 67108864,
+ "type": "EioProcess"
+ }
+ ],
+ "name": "cpu",
+ "dtb": {
+ "name": "dtb",
+ "eventq_index": 0,
+ "cxx_class": "AlphaISA::TLB",
+ "path": "system.cpu.dtb",
+ "type": "AlphaTLB",
+ "size": 64
+ },
+ "max_insts_any_thread": 500000,
+ "simulate_inst_stalls": false,
+ "progress_interval": 0.0,
+ "dcache_port": {
+ "peer": "system.membus.slave[2]",
+ "role": "MASTER"
+ },
+ "max_loads_any_thread": 0,
+ "tracer": {
+ "eventq_index": 0,
+ "path": "system.cpu.tracer",
+ "type": "ExeTracer",
+ "name": "tracer",
+ "cxx_class": "Trace::ExeTracer"
+ }
+ }
+ ],
+ "work_begin_cpu_id_exit": -1
+ },
+ "time_sync_period": 0.1,
+ "eventq_index": 0,
+ "time_sync_spin_threshold": 9.999999999999999e-05,
+ "cxx_class": "Root",
+ "path": "root",
+ "time_sync_enable": false,
+ "type": "Root",
+ "full_system": false
+}
\ No newline at end of file
diff -r 9eab5efc02e8 -r cc6408469397
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout Fri May
09 18:58:50 2014 -0400
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout Sat May
10 22:13:51 2014 -0400
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 27 2014 00:31:18
-gem5 started Jan 27 2014 00:31:45
+gem5 compiled May 10 2014 16:25:16
+gem5 started May 10 2014 16:56:07
gem5 executing on zizzer
-command line: build/ALPHA/gem5.opt -d
build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re
tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic
+command line: build/ALPHA/gem5.opt -d
build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re
/z/stever/hg/gem5/tests/run.py
build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
main dictionary has 1245 entries
diff -r 9eab5efc02e8 -r cc6408469397
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt Fri May
09 18:58:50 2014 -0400
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt Sat May
10 22:13:51 2014 -0400
@@ -4,11 +4,11 @@
sim_ticks 250015500 #
Number of ticks simulated
final_tick 250015500 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 1916007 #
Simulator instruction rate (inst/s)
-host_op_rate 1915868 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 957925931 #
Simulator tick rate (ticks/s)
-host_mem_usage 266944 #
Number of bytes of host memory used
-host_seconds 0.26 #
Real time elapsed on the host
+host_inst_rate 2753718 #
Simulator instruction rate (inst/s)
+host_op_rate 2753463 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1376691607 #
Simulator tick rate (ticks/s)
+host_mem_usage 219892 #
Number of bytes of host memory used
+host_seconds 0.18 #
Real time elapsed on the host
sim_insts 500001 #
Number of instructions simulated
sim_ops 500001 #
Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 #
Voltage in Volts
@@ -95,5 +95,40 @@
system.cpu.not_idle_fraction 1 #
Percentage of non-idle cycles
system.cpu.idle_fraction 0 #
Percentage of idle cycles
system.cpu.Branches 59023 #
Number of branches fetched
+system.cpu.op_class::No_OpClass 18814 3.76% 3.76% #
Class of executed instruction
+system.cpu.op_class::IntAlu 300388 60.08% 63.84% #
Class of executed instruction
+system.cpu.op_class::IntMult 10 0.00% 63.84% #
Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 63.84% #
Class of executed instruction
+system.cpu.op_class::FloatAdd 10 0.00% 63.84% #
Class of executed instruction
+system.cpu.op_class::FloatCmp 2 0.00% 63.84% #
Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 63.84% #
Class of executed instruction
+system.cpu.op_class::FloatMult 2 0.00% 63.84% #
Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 63.84% #
Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 63.84% #
Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 63.84% #
Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% #
Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 63.84% #
Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 63.84% #
Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 63.84% #
Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 63.84% #
Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 63.84% #
Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% #
Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 63.84% #
Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% #
Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 63.84% #
Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% #
Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% #
Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% #
Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% #
Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% #
Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% #
Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% #
Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% #
Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% #
Class of executed instruction
+system.cpu.op_class::MemRead 124443 24.89% 88.73% #
Class of executed instruction
+system.cpu.op_class::MemWrite 56350 11.27% 100.00% #
Class of executed instruction
+system.cpu.op_class::IprAccess 0 0.00% 100.00% #
Class of executed instruction
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00% #
Class of executed instruction
+system.cpu.op_class::total 500019 #
Class of executed instruction
---------- End Simulation Statistics ----------
diff -r 9eab5efc02e8 -r cc6408469397
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
Fri May 09 18:58:50 2014 -0400
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
Sat May 10 22:13:51 2014 -0400
@@ -43,6 +43,7 @@
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
@@ -64,6 +65,7 @@
_______________________________________________
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