changeset cfb6b578a89a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=cfb6b578a89a
description:
arm: make the bi-mode predictor the default for O3_ARM_v7a_BP
the branch predictor used in the Cortex-A15 is a bi-mode style
predictor,
see:
http://arm.com/files/pdf/at-exploring_the_design_of_the_cortex-a15.pdf
and
http://nvidia.com/docs/IO/116757/NVIDIA_Quad_a15_whitepaper_FINALv2.pdf
this patch makes the bi-mode predictor the default for the ARM O3 CPU.
diffstat:
configs/common/O3_ARM_v7a.py | 11 ++++-------
1 files changed, 4 insertions(+), 7 deletions(-)
diffs (36 lines):
diff -r cb4e86c17767 -r cfb6b578a89a configs/common/O3_ARM_v7a.py
--- a/configs/common/O3_ARM_v7a.py Sun Jun 22 14:33:09 2014 -0700
+++ b/configs/common/O3_ARM_v7a.py Mon Jun 30 13:50:01 2014 -0400
@@ -42,7 +42,7 @@
count = 1
-# Floating point and SIMD instructions
+# Floating point and SIMD instructions
class O3_ARM_v7a_FP(FUDesc):
opList = [ OpDesc(opClass='SimdAdd', opLat=4),
OpDesc(opClass='SimdAddAcc', opLat=4),
@@ -87,12 +87,9 @@
FUList = [O3_ARM_v7a_Simple_Int(), O3_ARM_v7a_Complex_Int(),
O3_ARM_v7a_Load(), O3_ARM_v7a_Store(), O3_ARM_v7a_FP()]
-# Tournament Branch Predictor
+# Bi-Mode Branch Predictor
class O3_ARM_v7a_BP(BranchPredictor):
- predType = "tournament"
- localPredictorSize = 2048
- localCtrBits = 2
- localHistoryTableSize = 1024
+ predType = "bi-mode"
globalPredictorSize = 8192
globalCtrBits = 2
choicePredictorSize = 8192
@@ -167,7 +164,7 @@
write_buffers = 16
is_top_level = 'true'
-# TLB Cache
+# TLB Cache
# Use a cache as a L2 TLB
class O3_ARM_v7aWalkCache(BaseCache):
hit_latency = 4
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