changeset ebb376f73dd2 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ebb376f73dd2
description:
cpu: `Minor' in-order CPU model
This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).
The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).
Documentation for the model can be found in
src/doc/inside-minor.doxygen and
its internal operations can be visualised using the Minorview tool
utils/minorview.py.
Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.
Minor is faster than the o3 model. Sample results:
Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036
diffstat:
build_opts/ALPHA | 2 +-
build_opts/ARM | 2 +-
configs/common/CpuConfig.py | 1 +
src/base/trace.hh | 14 +
src/cpu/SConscript | 2 +
src/cpu/TimingExpr.py | 176 ++++
src/cpu/minor/MinorCPU.py | 274 ++++++
src/cpu/minor/SConscript | 73 +
src/cpu/minor/SConsopts | 45 +
src/cpu/minor/activity.cc | 66 +
src/cpu/minor/activity.hh | 72 +
src/cpu/minor/buffers.hh | 653 +++++++++++++++
src/cpu/minor/cpu.cc | 362 ++++++++
src/cpu/minor/cpu.hh | 197 ++++
src/cpu/minor/decode.cc | 295 ++++++
src/cpu/minor/decode.hh | 138 +++
src/cpu/minor/dyn_inst.cc | 227 +++++
src/cpu/minor/dyn_inst.hh | 281 ++++++
src/cpu/minor/exec_context.hh | 350 ++++++++
src/cpu/minor/execute.cc | 1736 +++++++++++++++++++++++++++++++++++++++++
src/cpu/minor/execute.hh | 321 +++++++
src/cpu/minor/fetch1.cc | 676 +++++++++++++++
src/cpu/minor/fetch1.hh | 381 ++++++++
src/cpu/minor/fetch2.cc | 543 ++++++++++++
src/cpu/minor/fetch2.hh | 184 ++++
src/cpu/minor/func_unit.cc | 242 +++++
src/cpu/minor/func_unit.hh | 268 ++++++
src/cpu/minor/lsq.cc | 1614 ++++++++++++++++++++++++++++++++++++++
src/cpu/minor/lsq.hh | 722 +++++++++++++++++
src/cpu/minor/pipe_data.cc | 294 ++++++
src/cpu/minor/pipe_data.hh | 288 ++++++
src/cpu/minor/pipeline.cc | 250 +++++
src/cpu/minor/pipeline.hh | 145 +++
src/cpu/minor/scoreboard.cc | 323 +++++++
src/cpu/minor/scoreboard.hh | 145 +++
src/cpu/minor/stats.cc | 87 ++
src/cpu/minor/stats.hh | 88 ++
src/cpu/minor/trace.hh | 75 +
src/cpu/pred/SConscript | 3 +-
src/cpu/static_inst.hh | 5 +
src/cpu/timing_expr.cc | 248 +++++
src/cpu/timing_expr.hh | 216 +++++
src/doc/inside-minor.doxygen | 1091 +++++++++++++++++++++++++
src/sim/SConscript | 2 +
src/sim/TickedObject.py | 43 +
src/sim/ticked_object.cc | 116 ++
src/sim/ticked_object.hh | 191 ++++
util/minorview.py | 107 ++
util/minorview/__init__.py | 36 +
util/minorview/blobs.py | 461 ++++++++++
util/minorview/colours.py | 68 +
util/minorview/minor.pic | 154 +++
util/minorview/model.py | 1109 ++++++++++++++++++++++++++
util/minorview/parse.py | 109 ++
util/minorview/point.py | 78 +
util/minorview/view.py | 524 ++++++++++++
56 files changed, 16170 insertions(+), 3 deletions(-)
diffs (truncated from 16452 to 300 lines):
diff -r 23384aa97d85 -r ebb376f73dd2 build_opts/ALPHA
--- a/build_opts/ALPHA Sat Jul 19 19:04:58 2014 -0700
+++ b/build_opts/ALPHA Wed Jul 23 16:09:04 2014 -0500
@@ -1,4 +1,4 @@
TARGET_ISA = 'alpha'
SS_COMPATIBLE_FP = 1
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU,MinorCPU'
PROTOCOL = 'MI_example'
diff -r 23384aa97d85 -r ebb376f73dd2 build_opts/ARM
--- a/build_opts/ARM Sat Jul 19 19:04:58 2014 -0700
+++ b/build_opts/ARM Wed Jul 23 16:09:04 2014 -0500
@@ -1,3 +1,3 @@
TARGET_ISA = 'arm'
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU'
PROTOCOL = 'MI_example'
diff -r 23384aa97d85 -r ebb376f73dd2 configs/common/CpuConfig.py
--- a/configs/common/CpuConfig.py Sat Jul 19 19:04:58 2014 -0700
+++ b/configs/common/CpuConfig.py Wed Jul 23 16:09:04 2014 -0500
@@ -51,6 +51,7 @@
("timing", "TimingSimpleCPU"),
("atomic", "AtomicSimpleCPU"),
("inorder", "InOrderCPU"),
+ ("minor", "MinorCPU"),
("detailed", "DerivO3CPU"),
("kvm", ("ArmKvmCPU", "X86KvmCPU")),
]
diff -r 23384aa97d85 -r ebb376f73dd2 src/base/trace.hh
--- a/src/base/trace.hh Sat Jul 19 19:04:58 2014 -0700
+++ b/src/base/trace.hh Wed Jul 23 16:09:04 2014 -0500
@@ -72,6 +72,20 @@
inline const std::string &name() { return Trace::DefaultName; }
+// Interface for things with names. (cf. SimObject but without other
+// functionality). This is useful when using DPRINTF
+class Named
+{
+ protected:
+ const std::string _name;
+
+ public:
+ Named(const std::string &name_) : _name(name_) { }
+
+ public:
+ const std::string &name() const { return _name; }
+};
+
//
// DPRINTF is a debugging trace facility that allows one to
// selectively enable tracing statements. To use DPRINTF, there must
diff -r 23384aa97d85 -r ebb376f73dd2 src/cpu/SConscript
--- a/src/cpu/SConscript Sat Jul 19 19:04:58 2014 -0700
+++ b/src/cpu/SConscript Wed Jul 23 16:09:04 2014 -0500
@@ -106,6 +106,7 @@
SimObject('IntelTrace.py')
SimObject('IntrControl.py')
SimObject('NativeTrace.py')
+SimObject('TimingExpr.py')
Source('activity.cc')
Source('base.cc')
@@ -123,6 +124,7 @@
Source('simple_thread.cc')
Source('thread_context.cc')
Source('thread_state.cc')
+Source('timing_expr.cc')
if env['TARGET_ISA'] == 'sparc':
SimObject('LegionTrace.py')
diff -r 23384aa97d85 -r ebb376f73dd2 src/cpu/TimingExpr.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/cpu/TimingExpr.py Wed Jul 23 16:09:04 2014 -0500
@@ -0,0 +1,176 @@
+# Copyright (c) 2013-2014 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andrew Bardsley
+
+from m5.params import *
+from m5.SimObject import SimObject
+
+# These classes define an expression language over uint64_t with only
+# a few operators. This can be used to form expressions for the extra
+# delay required in variable execution time instructions.
+#
+# Expressions, in evaluation, will have access to the ThreadContext and
+# a StaticInst
+
+class TimingExpr(SimObject):
+ type = 'TimingExpr'
+ cxx_header = 'cpu/timing_expr.hh'
+ abstract = True;
+
+class TimingExprLiteral(TimingExpr):
+ """Literal 64 bit unsigned value"""
+ type = 'TimingExprLiteral'
+ cxx_header = 'cpu/timing_expr.hh'
+
+ value = Param.UInt64("literal value")
+
+ def set_params(self, value):
+ self.value = value
+ return self
+
+class TimingExpr0(TimingExprLiteral):
+ """Convenient 0"""
+ value = 0
+
+class TimingExprSrcReg(TimingExpr):
+ """Find the source register number from the current inst"""
+ type = 'TimingExprSrcReg'
+ cxx_header = 'cpu/timing_expr.hh'
+
+ # index = Param.Unsigned("index into inst src regs")
+ index = Param.Unsigned("index into inst src regs")
+
+ def set_params(self, index):
+ self.index = index
+ return self
+
+class TimingExprReadIntReg(TimingExpr):
+ """Read an architectural register"""
+ type = 'TimingExprReadIntReg'
+ cxx_header = 'cpu/timing_expr.hh'
+
+ reg = Param.TimingExpr("register raw index to read")
+
+ def set_params(self, reg):
+ self.reg = reg
+ return self
+
+class TimingExprLet(TimingExpr):
+ """Block of declarations"""
+ type = 'TimingExprLet'
+ cxx_header = 'cpu/timing_expr.hh'
+
+ defns = VectorParam.TimingExpr("expressions for bindings")
+ expr = Param.TimingExpr("body expression")
+
+ def set_params(self, defns, expr):
+ self.defns = defns
+ self.expr = expr
+ return self
+
+class TimingExprRef(TimingExpr):
+ """Value of a bound sub-expression"""
+ type = 'TimingExprRef'
+ cxx_header = 'cpu/timing_expr.hh'
+
+ index = Param.Unsigned("expression index")
+
+ def set_params(self, index):
+ self.index = index
+ return self
+
+class TimingExprOp(Enum):
+ vals = [
+ 'timingExprAdd', 'timingExprSub',
+ 'timingExprUMul', 'timingExprUDiv',
+ 'timingExprSMul', 'timingExprSDiv',
+ 'timingExprUCeilDiv', # Unsigned divide rounding up
+ 'timingExprEqual', 'timingExprNotEqual',
+ 'timingExprULessThan',
+ 'timingExprUGreaterThan',
+ 'timingExprSLessThan',
+ 'timingExprSGreaterThan',
+ 'timingExprInvert',
+ 'timingExprNot',
+ 'timingExprAnd',
+ 'timingExprOr',
+ 'timingExprSizeInBits',
+ 'timingExprSignExtend32To64',
+ 'timingExprAbs'
+ ]
+
+class TimingExprUn(TimingExpr):
+ """Unary operator"""
+ type = 'TimingExprUn'
+ cxx_header = 'cpu/timing_expr.hh'
+
+ op = Param.TimingExprOp("operator")
+ arg = Param.TimingExpr("expression")
+
+ def set_params(self, op, arg):
+ self.op = op
+ self.arg = arg
+ return self
+
+class TimingExprBin(TimingExpr):
+ """Binary operator"""
+ type = 'TimingExprBin'
+ cxx_header = 'cpu/timing_expr.hh'
+
+ op = Param.TimingExprOp("operator")
+ left = Param.TimingExpr("LHS expression")
+ right = Param.TimingExpr("RHS expression")
+
+ def set_params(self, op, left, right):
+ self.op = op
+ self.left = left
+ self.right = right
+ return self
+
+class TimingExprIf(TimingExpr):
+ """If-then-else operator"""
+ type = 'TimingExprIf'
+ cxx_header = 'cpu/timing_expr.hh'
+
+ cond = Param.TimingExpr("condition expression")
+ trueExpr = Param.TimingExpr("true expression")
+ falseExpr = Param.TimingExpr("false expression")
+
+ def set_params(self, cond, trueExpr, falseExpr):
+ self.cond = cond
+ self.trueExpr = trueExpr
+ self.falseExpr = falseExpr
+ return self
diff -r 23384aa97d85 -r ebb376f73dd2 src/cpu/minor/MinorCPU.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/cpu/minor/MinorCPU.py Wed Jul 23 16:09:04 2014 -0500
@@ -0,0 +1,274 @@
+# Copyright (c) 2012-2014 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+# Nathan Binkert
+# Andrew Bardsley
+
+from m5.defines import buildEnv
+from m5.params import *
+from m5.proxy import *
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