changeset 79fde1c67ed8 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=79fde1c67ed8 description: arm: change MISCREG_L2ERRSR to warn not fail
Some newer binaries compiled for Versatile Express TC2 contain access to implementation specific L2MERRSR registers. This causes an infinite loop of undefined exceptions. This patch changes the behavior to "warn not fail" to keep the workloads going. diffstat: src/arch/arm/miscregs.cc | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diffs (21 lines): diff -r 3ea92bc6393b -r 79fde1c67ed8 src/arch/arm/miscregs.cc --- a/src/arch/arm/miscregs.cc Wed Aug 13 06:57:35 2014 -0400 +++ b/src/arch/arm/miscregs.cc Wed Aug 13 06:57:36 2014 -0400 @@ -770,7 +770,7 @@ // MISCREG_CPUMERRSR bitset<NUM_MISCREG_INFOS>(string("1111111111000000000")), // MISCREG_L2MERRSR - bitset<NUM_MISCREG_INFOS>(string("1111111111000000000")), + bitset<NUM_MISCREG_INFOS>(string("1111111111000000010")), // AArch64 registers (Op0=2) // MISCREG_MDCCINT_EL1 @@ -1330,7 +1330,7 @@ // MISCREG_CPUMERRSR_EL1 bitset<NUM_MISCREG_INFOS>(string("1111111111000000001")), // MISCREG_L2MERRSR_EL1 - bitset<NUM_MISCREG_INFOS>(string("1111111111000000001")), + bitset<NUM_MISCREG_INFOS>(string("1111111111000000010")), // MISCREG_CBAR_EL1 bitset<NUM_MISCREG_INFOS>(string("0101010101000000001")), _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev