----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2325/ -----------------------------------------------------------
Review request for Default. Repository: gem5 Description ------- Changeset 10285:218ddd25c88c --------------------------- mem: Fix address interleaving bug in DRAM controller This patch fixes a bug in the DRAM controller address decoding. In cases where the DRAM burst size was smaller than the interleaving stripe size (e.g. LPDDR3 x32 with a 64 byte cache line) one address bit effectively got used as a channel bit when it should have been a low-order column bit. This patch adds a notion of "columns per stripe", and more clearly deals with the low-order column bits and high-order column bits. The patch also relaxes the granularity check such that it is possible to use interleaving granularities other than the cache line size. The patch also adds a missing M5_CLASS_VAR_USED to the tCK member as it is only used in the debug build for now. Diffs ----- src/mem/dram_ctrl.hh 79fde1c67ed8 src/mem/dram_ctrl.cc 79fde1c67ed8 Diff: http://reviews.gem5.org/r/2325/diff/ Testing ------- Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
