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Ship it! src/arch/arm/ccregs.hh <http://reviews.gem5.org/r/2337/#comment4800> There is inconsistency in the positioning of braces. - Nilay Vaish On Aug. 13, 2014, 2:07 p.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2337/ > ----------------------------------------------------------- > > (Updated Aug. 13, 2014, 2:07 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10304:3739aea2f79e > --------------------------- > arm: use condition code registers for ARM ISA > > Analogous to ee049bf (for x86). Requires a bump of the checkpoint version > and corresponding upgrader code to move the condition code register values > to the new register file. > > > Diffs > ----- > > src/arch/arm/ccregs.hh PRE-CREATION > src/arch/arm/faults.cc 79fde1c67ed8 > src/arch/arm/insts/static_inst.cc 79fde1c67ed8 > src/arch/arm/intregs.hh 79fde1c67ed8 > src/arch/arm/isa.hh 79fde1c67ed8 > src/arch/arm/isa.cc 79fde1c67ed8 > src/arch/arm/isa/operands.isa 79fde1c67ed8 > src/arch/arm/miscregs.hh 79fde1c67ed8 > src/arch/arm/nativetrace.cc 79fde1c67ed8 > src/arch/arm/registers.hh 79fde1c67ed8 > src/arch/arm/utility.cc 79fde1c67ed8 > src/cpu/o3/O3CPU.py 79fde1c67ed8 > src/cpu/simple_thread.hh 79fde1c67ed8 > src/sim/serialize.hh 79fde1c67ed8 > util/cpt_upgrader.py 79fde1c67ed8 > > Diff: http://reviews.gem5.org/r/2337/diff/ > > > Testing > ------- > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
