-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/2367/
-----------------------------------------------------------

Review request for Default.


Repository: gem5


Description
-------

Changeset 10318:f99394b416bb
---------------------------
cpu: Fix o3 drain bug

For X86, the o3 CPU would get stuck with the commit stage not being
drained if an interrupt arrived while drain was pending. isDrained()
makes sure that pcState.microPC() == 0, thus ensuring that we are at
an instruction boundary. However, when we take an interrupt we
execute:

    pcState.upc(romMicroPC(entry));
    pcState.nupc(romMicroPC(entry) + 1);
    tc->pcState(pcState);

As a result, the MicroPC is no longer zero. This patch ensures the drain is
delayed until no interrupts are present.  Once draining, non-synchronous
interrupts are deffered until after the switch.


Diffs
-----

  src/cpu/o3/commit.hh 2a1d75864ad2 
  src/cpu/o3/commit_impl.hh 2a1d75864ad2 

Diff: http://reviews.gem5.org/r/2367/diff/


Testing
-------

Regressions pass.


Thanks,

Andreas Hansson

_______________________________________________
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

Reply via email to