changeset 5b6279635c49 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=5b6279635c49
description:
cpu: Change writeback modeling for outstanding instructions
As highlighed on the mailing list gem5's writeback modeling can impact
performance. This patch removes the limitation on maximum outstanding
issued
instructions, however the number that can writeback in a single cycle
is still
respected in instToCommit().
diffstat:
configs/common/O3_ARM_v7a.py | 1 -
src/cpu/o3/O3CPU.py | 1 -
src/cpu/o3/iew.hh | 53 -------------------------------------------
src/cpu/o3/iew_impl.hh | 10 --------
src/cpu/o3/inst_queue_impl.hh | 2 -
src/cpu/o3/lsq_unit.hh | 7 -----
src/cpu/o3/lsq_unit_impl.hh | 5 +---
7 files changed, 1 insertions(+), 78 deletions(-)
diffs (210 lines):
diff -r 43516d8eabe9 -r 5b6279635c49 configs/common/O3_ARM_v7a.py
--- a/configs/common/O3_ARM_v7a.py Wed Sep 03 07:42:32 2014 -0400
+++ b/configs/common/O3_ARM_v7a.py Wed Sep 03 07:42:33 2014 -0400
@@ -126,7 +126,6 @@
dispatchWidth = 6
issueWidth = 8
wbWidth = 8
- wbDepth = 1
fuPool = O3_ARM_v7a_FUP()
iewToCommitDelay = 1
renameToROBDelay = 1
diff -r 43516d8eabe9 -r 5b6279635c49 src/cpu/o3/O3CPU.py
--- a/src/cpu/o3/O3CPU.py Wed Sep 03 07:42:32 2014 -0400
+++ b/src/cpu/o3/O3CPU.py Wed Sep 03 07:42:33 2014 -0400
@@ -84,7 +84,6 @@
dispatchWidth = Param.Unsigned(8, "Dispatch width")
issueWidth = Param.Unsigned(8, "Issue width")
wbWidth = Param.Unsigned(8, "Writeback width")
- wbDepth = Param.Unsigned(1, "Writeback depth")
fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool")
iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit "
diff -r 43516d8eabe9 -r 5b6279635c49 src/cpu/o3/iew.hh
--- a/src/cpu/o3/iew.hh Wed Sep 03 07:42:32 2014 -0400
+++ b/src/cpu/o3/iew.hh Wed Sep 03 07:42:33 2014 -0400
@@ -219,49 +219,6 @@
/** Returns if the LSQ has any stores to writeback. */
bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); }
- void incrWb(InstSeqNum &sn)
- {
- ++wbOutstanding;
- if (wbOutstanding == wbMax)
- ableToIssue = false;
- DPRINTF(IEW, "wbOutstanding: %i [sn:%lli]\n", wbOutstanding, sn);
- assert(wbOutstanding <= wbMax);
-#ifdef DEBUG
- wbList.insert(sn);
-#endif
- }
-
- void decrWb(InstSeqNum &sn)
- {
- if (wbOutstanding == wbMax)
- ableToIssue = true;
- wbOutstanding--;
- DPRINTF(IEW, "wbOutstanding: %i [sn:%lli]\n", wbOutstanding, sn);
- assert(wbOutstanding >= 0);
-#ifdef DEBUG
- assert(wbList.find(sn) != wbList.end());
- wbList.erase(sn);
-#endif
- }
-
-#ifdef DEBUG
- std::set<InstSeqNum> wbList;
-
- void dumpWb()
- {
- std::set<InstSeqNum>::iterator wb_it = wbList.begin();
- while (wb_it != wbList.end()) {
- cprintf("[sn:%lli]\n",
- (*wb_it));
- wb_it++;
- }
- }
-#endif
-
- bool canIssue() { return ableToIssue; }
-
- bool ableToIssue;
-
/** Check misprediction */
void checkMisprediction(DynInstPtr &inst);
@@ -452,19 +409,9 @@
*/
unsigned wbCycle;
- /** Number of instructions in flight that will writeback. */
-
- /** Number of instructions in flight that will writeback. */
- int wbOutstanding;
-
/** Writeback width. */
unsigned wbWidth;
- /** Writeback width * writeback depth, where writeback depth is
- * the number of cycles of writing back instructions that can be
- * buffered. */
- unsigned wbMax;
-
/** Number of active threads. */
ThreadID numThreads;
diff -r 43516d8eabe9 -r 5b6279635c49 src/cpu/o3/iew_impl.hh
--- a/src/cpu/o3/iew_impl.hh Wed Sep 03 07:42:32 2014 -0400
+++ b/src/cpu/o3/iew_impl.hh Wed Sep 03 07:42:33 2014 -0400
@@ -76,7 +76,6 @@
issueToExecuteDelay(params->issueToExecuteDelay),
dispatchWidth(params->dispatchWidth),
issueWidth(params->issueWidth),
- wbOutstanding(0),
wbWidth(params->wbWidth),
numThreads(params->numThreads)
{
@@ -109,12 +108,8 @@
fetchRedirect[tid] = false;
}
- wbMax = wbWidth * params->wbDepth;
-
updateLSQNextCycle = false;
- ableToIssue = true;
-
skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) +
issueWidth;
}
@@ -635,8 +630,6 @@
++wbCycle;
wbNumInst = 0;
}
-
- assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
}
DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
@@ -1263,7 +1256,6 @@
++iewExecSquashedInsts;
- decrWb(inst->seqNum);
continue;
}
@@ -1502,8 +1494,6 @@
}
writebackCount[tid]++;
}
-
- decrWb(inst->seqNum);
}
}
diff -r 43516d8eabe9 -r 5b6279635c49 src/cpu/o3/inst_queue_impl.hh
--- a/src/cpu/o3/inst_queue_impl.hh Wed Sep 03 07:42:32 2014 -0400
+++ b/src/cpu/o3/inst_queue_impl.hh Wed Sep 03 07:42:33 2014 -0400
@@ -756,7 +756,6 @@
int total_issued = 0;
while (total_issued < (totalWidth - total_deferred_mem_issued) &&
- iewStage->canIssue() &&
order_it != order_end_it) {
OpClass op_class = (*order_it).queueType;
@@ -861,7 +860,6 @@
listOrder.erase(order_it++);
statIssuedInstType[tid][op_class]++;
- iewStage->incrWb(issuing_inst->seqNum);
} else {
statFuBusy[op_class]++;
fuBusy[tid]++;
diff -r 43516d8eabe9 -r 5b6279635c49 src/cpu/o3/lsq_unit.hh
--- a/src/cpu/o3/lsq_unit.hh Wed Sep 03 07:42:32 2014 -0400
+++ b/src/cpu/o3/lsq_unit.hh Wed Sep 03 07:42:33 2014 -0400
@@ -762,7 +762,6 @@
// Tell IQ/mem dep unit that this instruction will need to be
// rescheduled eventually
iewStage->rescheduleMemInst(load_inst);
- iewStage->decrWb(load_inst->seqNum);
load_inst->clearIssued();
++lsqRescheduledLoads;
@@ -889,12 +888,6 @@
++lsqCacheBlocked;
- // If the first part of a split access succeeds, then let the LSQ
- // handle the decrWb when completeDataAccess is called upon return
- // of the requested first part of data
- if (!completedFirst)
- iewStage->decrWb(load_inst->seqNum);
-
// There's an older load that's already going to squash.
if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum)
return NoFault;
diff -r 43516d8eabe9 -r 5b6279635c49 src/cpu/o3/lsq_unit_impl.hh
--- a/src/cpu/o3/lsq_unit_impl.hh Wed Sep 03 07:42:32 2014 -0400
+++ b/src/cpu/o3/lsq_unit_impl.hh Wed Sep 03 07:42:33 2014 -0400
@@ -109,9 +109,7 @@
}
assert(!cpu->switchedOut());
- if (inst->isSquashed()) {
- iewStage->decrWb(inst->seqNum);
- } else {
+ if (!inst->isSquashed()) {
if (!state->noWB) {
if (!TheISA::HasUnalignedMemAcc || !state->isSplit ||
!state->isLoad) {
@@ -1130,7 +1128,6 @@
// Squashed instructions do not need to complete their access.
if (inst->isSquashed()) {
- iewStage->decrWb(inst->seqNum);
assert(!inst->isStore());
++lsqIgnoredResponses;
return;
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