changeset 8bee5f4edb92 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=8bee5f4edb92
description:
arm: use condition code registers for ARM ISA
Analogous to ee049bf (for x86). Requires a bump of the checkpoint
version
and corresponding upgrader code to move the condition code register
values
to the new register file.
diffstat:
src/arch/arm/ccregs.hh | 85 +++++++++++++++++++++++++++++++++++++++
src/arch/arm/faults.cc | 18 ++++----
src/arch/arm/insts/static_inst.cc | 5 +-
src/arch/arm/intregs.hh | 5 --
src/arch/arm/isa.cc | 14 +++---
src/arch/arm/isa.hh | 6 +-
src/arch/arm/isa/operands.isa | 54 ++++++++++++------------
src/arch/arm/miscregs.hh | 19 --------
src/arch/arm/nativetrace.cc | 12 ++--
src/arch/arm/registers.hh | 14 ++++--
src/arch/arm/utility.cc | 6 +-
src/cpu/o3/O3CPU.py | 2 +-
src/cpu/simple_thread.hh | 1 +
src/sim/serialize.hh | 2 +-
util/cpt_upgrader.py | 28 ++++++++++++
15 files changed, 184 insertions(+), 87 deletions(-)
diffs (truncated from 538 to 300 lines):
diff -r 85001c018d4c -r 8bee5f4edb92 src/arch/arm/ccregs.hh
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/arm/ccregs.hh Tue Apr 29 16:05:02 2014 -0500
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2014 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Curtis Dunham
+ */
+#ifndef __ARCH_ARM_CCREGS_HH__
+#define __ARCH_ARM_CCREGS_HH__
+
+namespace ArmISA
+{
+
+enum ccRegIndex {
+ CCREG_NZ,
+ CCREG_C,
+ CCREG_V,
+ CCREG_GE,
+ CCREG_FP,
+ CCREG_ZERO,
+ NUM_CCREGS
+};
+
+const char * const ccRegName[NUM_CCREGS] = {
+ "nz",
+ "c",
+ "v",
+ "ge",
+ "fp",
+ "zero"
+};
+
+enum ConditionCode {
+ COND_EQ = 0,
+ COND_NE, // 1
+ COND_CS, // 2
+ COND_CC, // 3
+ COND_MI, // 4
+ COND_PL, // 5
+ COND_VS, // 6
+ COND_VC, // 7
+ COND_HI, // 8
+ COND_LS, // 9
+ COND_GE, // 10
+ COND_LT, // 11
+ COND_GT, // 12
+ COND_LE, // 13
+ COND_AL, // 14
+ COND_UC // 15
+};
+
+}
+
+#endif // __ARCH_ARM_CCREGS_HH__
diff -r 85001c018d4c -r 8bee5f4edb92 src/arch/arm/faults.cc
--- a/src/arch/arm/faults.cc Wed Sep 03 07:42:43 2014 -0400
+++ b/src/arch/arm/faults.cc Tue Apr 29 16:05:02 2014 -0500
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2012-2013 ARM Limited
+ * Copyright (c) 2010, 2012-2014 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -466,10 +466,10 @@
SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
SCR scr = tc->readMiscReg(MISCREG_SCR);
CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR);
- saved_cpsr.nz = tc->readIntReg(INTREG_CONDCODES_NZ);
- saved_cpsr.c = tc->readIntReg(INTREG_CONDCODES_C);
- saved_cpsr.v = tc->readIntReg(INTREG_CONDCODES_V);
- saved_cpsr.ge = tc->readIntReg(INTREG_CONDCODES_GE);
+ saved_cpsr.nz = tc->readCCReg(CCREG_NZ);
+ saved_cpsr.c = tc->readCCReg(CCREG_C);
+ saved_cpsr.v = tc->readCCReg(CCREG_V);
+ saved_cpsr.ge = tc->readCCReg(CCREG_GE);
Addr curPc M5_VAR_USED = tc->pcState().pc();
ITSTATE it = tc->pcState().itstate();
@@ -615,9 +615,9 @@
// Save process state into SPSR_ELx
CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
CPSR spsr = cpsr;
- spsr.nz = tc->readIntReg(INTREG_CONDCODES_NZ);
- spsr.c = tc->readIntReg(INTREG_CONDCODES_C);
- spsr.v = tc->readIntReg(INTREG_CONDCODES_V);
+ spsr.nz = tc->readCCReg(CCREG_NZ);
+ spsr.c = tc->readCCReg(CCREG_C);
+ spsr.v = tc->readCCReg(CCREG_V);
if (from64) {
// Force some bitfields to 0
spsr.q = 0;
@@ -628,7 +628,7 @@
spsr.it2 = 0;
spsr.t = 0;
} else {
- spsr.ge = tc->readIntReg(INTREG_CONDCODES_GE);
+ spsr.ge = tc->readCCReg(CCREG_GE);
ITSTATE it = tc->pcState().itstate();
spsr.it2 = it.top6;
spsr.it1 = it.bottom2;
diff -r 85001c018d4c -r 8bee5f4edb92 src/arch/arm/insts/static_inst.cc
--- a/src/arch/arm/insts/static_inst.cc Wed Sep 03 07:42:43 2014 -0400
+++ b/src/arch/arm/insts/static_inst.cc Tue Apr 29 16:05:02 2014 -0500
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2013 ARM Limited
+ * Copyright (c) 2010-2014 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -335,7 +335,8 @@
ccprintf(os, "%s", ArmISA::miscRegName[rel_reg]);
break;
case CCRegClass:
- panic("printReg: CCRegClass but ARM has no CC regs\n");
+ ccprintf(os, "cc_%s", ArmISA::ccRegName[rel_reg]);
+ break;
}
}
diff -r 85001c018d4c -r 8bee5f4edb92 src/arch/arm/intregs.hh
--- a/src/arch/arm/intregs.hh Wed Sep 03 07:42:43 2014 -0400
+++ b/src/arch/arm/intregs.hh Tue Apr 29 16:05:02 2014 -0500
@@ -115,11 +115,6 @@
INTREG_UREG0,
INTREG_UREG1,
INTREG_UREG2,
- INTREG_CONDCODES_NZ,
- INTREG_CONDCODES_C,
- INTREG_CONDCODES_V,
- INTREG_CONDCODES_GE,
- INTREG_FPCONDCODES,
INTREG_DUMMY, // Dummy reg used to throw away int reg results
INTREG_SP0,
diff -r 85001c018d4c -r 8bee5f4edb92 src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc Wed Sep 03 07:42:43 2014 -0400
+++ b/src/arch/arm/isa.cc Tue Apr 29 16:05:02 2014 -0500
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2013 ARM Limited
+ * Copyright (c) 2010-2014 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -599,9 +599,9 @@
case MISCREG_NZCV:
{
CPSR cpsr = 0;
- cpsr.nz = tc->readIntReg(INTREG_CONDCODES_NZ);
- cpsr.c = tc->readIntReg(INTREG_CONDCODES_C);
- cpsr.v = tc->readIntReg(INTREG_CONDCODES_V);
+ cpsr.nz = tc->readCCReg(CCREG_NZ);
+ cpsr.c = tc->readCCReg(CCREG_C);
+ cpsr.v = tc->readCCReg(CCREG_V);
return cpsr;
}
case MISCREG_DAIF:
@@ -1688,9 +1688,9 @@
{
CPSR cpsr = val;
- tc->setIntReg(INTREG_CONDCODES_NZ, cpsr.nz);
- tc->setIntReg(INTREG_CONDCODES_C, cpsr.c);
- tc->setIntReg(INTREG_CONDCODES_V, cpsr.v);
+ tc->setCCReg(CCREG_NZ, cpsr.nz);
+ tc->setCCReg(CCREG_C, cpsr.c);
+ tc->setCCReg(CCREG_V, cpsr.v);
}
break;
case MISCREG_DAIF:
diff -r 85001c018d4c -r 8bee5f4edb92 src/arch/arm/isa.hh
--- a/src/arch/arm/isa.hh Wed Sep 03 07:42:43 2014 -0400
+++ b/src/arch/arm/isa.hh Tue Apr 29 16:05:02 2014 -0500
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2012-2013 ARM Limited
+ * Copyright (c) 2010, 2012-2014 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -268,19 +268,21 @@
int
flattenFloatIndex(int reg) const
{
+ assert(reg >= 0);
return reg;
}
- // dummy
int
flattenCCIndex(int reg) const
{
+ assert(reg >= 0);
return reg;
}
int
flattenMiscIndex(int reg) const
{
+ assert(reg >= 0);
int flat_idx = reg;
if (reg == MISCREG_SPSR) {
diff -r 85001c018d4c -r 8bee5f4edb92 src/arch/arm/isa/operands.isa
--- a/src/arch/arm/isa/operands.isa Wed Sep 03 07:42:43 2014 -0400
+++ b/src/arch/arm/isa/operands.isa Tue Apr 29 16:05:02 2014 -0500
@@ -1,5 +1,5 @@
// -*- mode:c++ -*-
-// Copyright (c) 2010-2013 ARM Limited
+// Copyright (c) 2010-2014 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -151,8 +151,8 @@
return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
maybePCRead, maybeAIWPCWrite)
- def intRegCC(idx):
- return ('IntReg', 'uw', idx, None, srtNormal)
+ def ccReg(idx):
+ return ('CCReg', 'uw', idx, None, srtNormal)
def cntrlReg(idx, id = srtNormal, type = 'uw'):
return ('ControlReg', type, idx, None, id)
@@ -221,31 +221,31 @@
'X2': intRegX64('2'),
'X3': intRegX64('3'),
- #Pseudo integer condition code registers
- 'CondCodesNZ': intRegCC('INTREG_CONDCODES_NZ'),
- 'CondCodesC': intRegCC('INTREG_CONDCODES_C'),
- 'CondCodesV': intRegCC('INTREG_CONDCODES_V'),
- 'CondCodesGE': intRegCC('INTREG_CONDCODES_GE'),
- 'OptCondCodesNZ': intRegCC(
- '''(condCode == COND_AL || condCode == COND_UC ||
- condCode == COND_CC || condCode == COND_CS ||
- condCode == COND_VS || condCode == COND_VC) ?
- INTREG_ZERO : INTREG_CONDCODES_NZ'''),
- 'OptCondCodesC': intRegCC(
- '''(condCode == COND_HI || condCode == COND_LS ||
+ # Condition code registers
+ 'CondCodesNZ': ccReg('CCREG_NZ'),
+ 'CondCodesC': ccReg('CCREG_C'),
+ 'CondCodesV': ccReg('CCREG_V'),
+ 'CondCodesGE': ccReg('CCREG_GE'),
+ 'OptCondCodesNZ': ccReg(
+ '''((condCode == COND_AL || condCode == COND_UC ||
+ condCode == COND_CC || condCode == COND_CS ||
+ condCode == COND_VS || condCode == COND_VC) ?
+ CCREG_ZERO : CCREG_NZ)'''),
+ 'OptCondCodesC': ccReg(
+ '''((condCode == COND_HI || condCode == COND_LS ||
condCode == COND_CS || condCode == COND_CC) ?
- INTREG_CONDCODES_C : INTREG_ZERO'''),
- 'OptShiftRmCondCodesC': intRegCC(
- '''(condCode == COND_HI || condCode == COND_LS ||
- condCode == COND_CS || condCode == COND_CC ||
- shiftType == ROR) ?
- INTREG_CONDCODES_C : INTREG_ZERO'''),
- 'OptCondCodesV': intRegCC(
- '''(condCode == COND_VS || condCode == COND_VC ||
- condCode == COND_GE || condCode == COND_LT ||
- condCode == COND_GT || condCode == COND_LE) ?
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