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(Updated Sept. 16, 2014, 3:37 p.m.) Review request for Default. Changes ------- Updated syscall and page fault handler. I am reposting this mainly for people to see how changes in http://reviews.gem5.org/r/2313/ are affecting this patch. Repository: gem5 Description (updated) ------- Changeset 10302:8bbfa3e4752c --------------------------- SegInit, x86: Segment initialization to support KvmCPU in SE This patch sets up low and high privilege code and data segments and places them in the following order: cs low, ds low, ds, cs, in the GDT. Additionally, a syscall and page fault handler for KvmCPU in SE mode are defined. The order of the segment selectors in GDT is required in this manner for interrupt handling to work properly. Segment initialization is done for all the thread contexts. Diffs (updated) ----- src/arch/x86/process.cc bec0c5ffc3237096570fe4c802aeb37e1e396d1b src/arch/x86/regs/misc.hh bec0c5ffc3237096570fe4c802aeb37e1e396d1b src/arch/x86/system.hh bec0c5ffc3237096570fe4c802aeb37e1e396d1b src/arch/x86/system.cc bec0c5ffc3237096570fe4c802aeb37e1e396d1b src/sim/Process.py bec0c5ffc3237096570fe4c802aeb37e1e396d1b src/sim/process.hh bec0c5ffc3237096570fe4c802aeb37e1e396d1b src/sim/process.cc bec0c5ffc3237096570fe4c802aeb37e1e396d1b Diff: http://reviews.gem5.org/r/2322/diff/ Testing ------- Quick regression tests Thanks, Alexandru Dutu _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
