changeset aa97958ce2aa in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=aa97958ce2aa
description:
mem: Clarify unit of DRAM controller buffer size
diffstat:
src/mem/DRAMCtrl.py | 5 ++++-
1 files changed, 4 insertions(+), 1 deletions(-)
diffs (15 lines):
diff -r 4ccec5baf82c -r aa97958ce2aa src/mem/DRAMCtrl.py
--- a/src/mem/DRAMCtrl.py Wed Nov 12 09:05:25 2014 -0500
+++ b/src/mem/DRAMCtrl.py Fri Nov 14 03:53:48 2014 -0500
@@ -71,7 +71,10 @@
# bus in front of the controller for multiple ports
port = SlavePort("Slave port")
- # the basic configuration of the controller architecture
+ # the basic configuration of the controller architecture, note
+ # that each entry corresponds to a burst for the specific DRAM
+ # configuration (e.g. x32 with burst length 8 is 32 bytes) and not
+ # the cacheline size or request/packet size
write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
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