changeset a4d0e8c2869c in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a4d0e8c2869c
description:
x86: pc: Put a stub IO device at port 0xed which the kernel can use for
delays.
There was already a stub device at 0x80, the port traditionally used
for an IO
delay. 0x80 is also the port used for POST codes sent by firmware, and
that
may have prompted adding this port as a second option.
diffstat:
src/dev/x86/Pc.py | 8 +++++---
1 files changed, 5 insertions(+), 3 deletions(-)
diffs (25 lines):
diff -r b61dc895269a -r a4d0e8c2869c src/dev/x86/Pc.py
--- a/src/dev/x86/Pc.py Tue Nov 18 19:17:29 2014 -0600
+++ b/src/dev/x86/Pc.py Fri Nov 21 17:22:02 2014 -0800
@@ -49,8 +49,9 @@
south_bridge = SouthBridge()
- # "Non-existant" port used for timing purposes by the linux kernel
- i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)
+ # "Non-existant" ports used for timing purposes by the linux kernel
+ i_dont_exist1 = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)
+ i_dont_exist2 = IsaFake(pio_addr=x86IOAddress(0xed), pio_size=1)
# Ports behind the pci config and data regsiters. These don't do anything,
# but the linux kernel fiddles with them anway.
@@ -71,7 +72,8 @@
def attachIO(self, bus, dma_ports = []):
self.south_bridge.attachIO(bus, dma_ports)
- self.i_dont_exist.pio = bus.master
+ self.i_dont_exist1.pio = bus.master
+ self.i_dont_exist2.pio = bus.master
self.behind_pci.pio = bus.master
self.com_1.pio = bus.master
self.fake_com_2.pio = bus.master
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