There are functions that correspond to this functionality although they’re poorly named for the purpose, but memWriteback() -> beginning of KVM simulation; memInvalidate -> end of KVM simulation. Another option would be to check for the memory time atomic_noncaching which I believe only KVM uses.
Ali On Nov 27, 2014, at 2:33 AM, Andreas Hansson via gem5-dev <[email protected]> wrote: > Hi Alex, > > Oh I was not suggesting you on your own should solve it, I merely think we > cannot just ignore the issue. > > I think the first thing is to establish an API around the switching of the > mode. I am happy to make the changes needed to the controller once we have > worked out the switching. > > Andreas > > On 11/26/14, 9:49 PM, "Dutu, Alexandru via gem5-dev" <[email protected]> > wrote: > >> Hi Andreas, >> >> Sorry for the late reply, I have missed your email. I will investigate >> more the issues with memory controller refresh events and let you know >> what I find out. >> >> Best regards, >> Alex >> _______________________________________________ >> gem5-dev mailing list >> [email protected] >> http://m5sim.org/mailman/listinfo/gem5-dev >> > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > > ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2557590 > ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2548782 > > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
