changeset 3b405d11d6dc in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3b405d11d6dc
description:
cpu: Move packet deallocation to recvTimingResp in the O3 CPU
Move the packet deallocations in the O3 CPU so that the
completeDataAccess
deals only with the LSQ specific parts and the generic recvTimingResp
frees the
packet in all other cases.
diffstat:
src/cpu/o3/lsq_impl.hh | 2 ++
src/cpu/o3/lsq_unit_impl.hh | 6 ------
2 files changed, 2 insertions(+), 6 deletions(-)
diffs (40 lines):
diff -r fc4c90a7d2f5 -r 3b405d11d6dc src/cpu/o3/lsq_impl.hh
--- a/src/cpu/o3/lsq_impl.hh Tue Dec 02 06:07:56 2014 -0500
+++ b/src/cpu/o3/lsq_impl.hh Tue Dec 02 06:07:58 2014 -0500
@@ -347,6 +347,8 @@
DPRINTF(LSQ, "Got error packet back for address: %#X\n",
pkt->getAddr());
thread[pkt->req->threadId()].completeDataAccess(pkt);
+ delete pkt->req;
+ delete pkt;
return true;
}
diff -r fc4c90a7d2f5 -r 3b405d11d6dc src/cpu/o3/lsq_unit_impl.hh
--- a/src/cpu/o3/lsq_unit_impl.hh Tue Dec 02 06:07:56 2014 -0500
+++ b/src/cpu/o3/lsq_unit_impl.hh Tue Dec 02 06:07:58 2014 -0500
@@ -105,15 +105,11 @@
DPRINTF(IEW, "[sn:%lli]: Response from first half of earlier "
"blocked split load recieved. Ignoring.\n", inst->seqNum);
delete state;
- delete pkt->req;
- delete pkt;
return;
}
// If this is a split access, wait until all packets are received.
if (TheISA::HasUnalignedMemAcc && !state->complete()) {
- delete pkt->req;
- delete pkt;
return;
}
@@ -142,8 +138,6 @@
cpu->ppDataAccessComplete->notify(std::make_pair(inst, pkt));
delete state;
- delete pkt->req;
- delete pkt;
}
template <class Impl>
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