changeset 1eec33d2fc52 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=1eec33d2fc52
description:
cpu: Only check for PC events on instruction boundaries.
Only the instruction address is actually checked, so there's no need to
check
repeatedly while we're working through the microops of a macroop and
that's
not changing.
diffstat:
src/cpu/o3/commit_impl.hh | 41 ++++++++++++++++++++++++-----------------
src/cpu/simple/atomic.cc | 6 ++++--
src/cpu/simple/timing.cc | 7 ++++---
3 files changed, 32 insertions(+), 22 deletions(-)
diffs (109 lines):
diff -r 25ecfc14f73f -r 1eec33d2fc52 src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh Fri Dec 05 01:44:24 2014 -0800
+++ b/src/cpu/o3/commit_impl.hh Fri Dec 05 01:47:35 2014 -0800
@@ -1,4 +1,5 @@
/*
+ * Copyright 2014 Google, Inc.
* Copyright (c) 2010-2014 ARM Limited
* All rights reserved
*
@@ -1105,20 +1106,27 @@
}
}
- int count = 0;
- Addr oldpc;
- // Debug statement. Checks to make sure we're not
- // currently updating state while handling PC events.
- assert(!thread[tid]->noSquashFromTC &&
!thread[tid]->trapPending);
- do {
- oldpc = pc[tid].instAddr();
- cpu->system->pcEventQueue.service(thread[tid]->getTC());
- count++;
- } while (oldpc != pc[tid].instAddr());
- if (count > 1) {
- DPRINTF(Commit,
- "PC skip function event, stopping commit\n");
- break;
+ bool onInstBoundary = !head_inst->isMicroop() ||
+ head_inst->isLastMicroop() ||
+ !head_inst->isDelayedCommit();
+
+ if (onInstBoundary) {
+ int count = 0;
+ Addr oldpc;
+ // Make sure we're not currently updating state while
+ // handling PC events.
+ assert(!thread[tid]->noSquashFromTC &&
+ !thread[tid]->trapPending);
+ do {
+ oldpc = pc[tid].instAddr();
+
cpu->system->pcEventQueue.service(thread[tid]->getTC());
+ count++;
+ } while (oldpc != pc[tid].instAddr());
+ if (count > 1) {
+ DPRINTF(Commit,
+ "PC skip function event, stopping commit\n");
+ break;
+ }
}
// Check if an instruction just enabled interrupts and we've
@@ -1128,9 +1136,8 @@
// case squash now to make sure the interrupt is handled.
//
// If we don't do this, we might end up in a live lock
situation
- if (!interrupt && avoidQuiesceLiveLock &&
- (!head_inst->isMicroop() || head_inst->isLastMicroop()) &&
- cpu->checkInterrupts(cpu->tcBase(0)))
+ if (!interrupt && avoidQuiesceLiveLock &&
+ onInstBoundary && cpu->checkInterrupts(cpu->tcBase(0)))
squashAfter(tid, head_inst);
} else {
DPRINTF(Commit, "Unable to commit head instruction PC:%s "
diff -r 25ecfc14f73f -r 1eec33d2fc52 src/cpu/simple/atomic.cc
--- a/src/cpu/simple/atomic.cc Fri Dec 05 01:44:24 2014 -0800
+++ b/src/cpu/simple/atomic.cc Fri Dec 05 01:47:35 2014 -0800
@@ -1,4 +1,5 @@
/*
+ * Copyright 2014 Google, Inc.
* Copyright (c) 2012-2013 ARM Limited
* All rights reserved.
*
@@ -518,10 +519,11 @@
numCycles++;
ppCycles->notify(1);
- if (!curStaticInst || !curStaticInst->isDelayedCommit())
+ if (!curStaticInst || !curStaticInst->isDelayedCommit()) {
checkForInterrupts();
+ checkPcEventQueue();
+ }
- checkPcEventQueue();
// We must have just got suspended by a PC event
if (_status == Idle) {
tryCompleteDrain();
diff -r 25ecfc14f73f -r 1eec33d2fc52 src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc Fri Dec 05 01:44:24 2014 -0800
+++ b/src/cpu/simple/timing.cc Fri Dec 05 01:47:35 2014 -0800
@@ -1,4 +1,5 @@
/*
+ * Copyright 2014 Google, Inc.
* Copyright (c) 2010-2013 ARM Limited
* All rights reserved
*
@@ -551,10 +552,10 @@
{
DPRINTF(SimpleCPU, "Fetch\n");
- if (!curStaticInst || !curStaticInst->isDelayedCommit())
+ if (!curStaticInst || !curStaticInst->isDelayedCommit()) {
checkForInterrupts();
-
- checkPcEventQueue();
+ checkPcEventQueue();
+ }
// We must have just got suspended by a PC event
if (_status == Idle)
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