changeset b9646f4546ad in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b9646f4546ad
description:
mem: Rework the structuring of the prefetchers
Re-organizes the prefetcher class structure. Previously the
BasePrefetcher forced multiple assumptions on the prefetchers that
inherited from it. This patch makes the BasePrefetcher class truly
representative of base functionality. For example, the base class no
longer enforces FIFO order. Instead, prefetchers with FIFO requests
(like the existing stride and tagged prefetchers) now inherit from a
new QueuedPrefetcher base class.
Finally, the stride-based prefetcher now assumes a custimizable lookup
table
(sets/ways) rather than the previous fully associative structure.
diffstat:
src/mem/cache/cache_impl.hh | 10 +-
src/mem/cache/prefetch/Prefetcher.py | 62 ++++---
src/mem/cache/prefetch/SConscript | 1 +
src/mem/cache/prefetch/base.cc | 258 ++++------------------------------
src/mem/cache/prefetch/base.hh | 139 +++++-------------
src/mem/cache/prefetch/queued.cc | 213 ++++++++++++++++++++++++++++
src/mem/cache/prefetch/queued.hh | 108 ++++++++++++++
src/mem/cache/prefetch/stride.cc | 205 +++++++++++++++-----------
src/mem/cache/prefetch/stride.hh | 55 +++---
src/mem/cache/prefetch/tagged.cc | 16 +-
src/mem/cache/prefetch/tagged.hh | 19 +-
11 files changed, 599 insertions(+), 487 deletions(-)
diffs (truncated from 1401 to 300 lines):
diff -r 0b969a35781f -r b9646f4546ad src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh Tue Dec 23 09:31:18 2014 -0500
+++ b/src/mem/cache/cache_impl.hh Tue Dec 23 09:31:18 2014 -0500
@@ -535,7 +535,7 @@
bool satisfied = access(pkt, blk, lat, writebacks);
// track time of availability of next prefetch, if any
- Tick next_pf_time = 0;
+ Tick next_pf_time = MaxTick;
bool needsResponse = pkt->needsResponse();
@@ -548,7 +548,7 @@
// Don't notify on SWPrefetch
if (!pkt->cmd.isSWPrefetch())
- next_pf_time = prefetcher->notify(pkt, time);
+ next_pf_time = prefetcher->notify(pkt);
}
if (needsResponse) {
@@ -648,7 +648,7 @@
if (prefetcher) {
// Don't notify on SWPrefetch
if (!pkt->cmd.isSWPrefetch())
- next_pf_time = prefetcher->notify(pkt, time);
+ next_pf_time = prefetcher->notify(pkt);
}
}
} else {
@@ -688,12 +688,12 @@
if (prefetcher) {
// Don't notify on SWPrefetch
if (!pkt->cmd.isSWPrefetch())
- next_pf_time = prefetcher->notify(pkt, time);
+ next_pf_time = prefetcher->notify(pkt);
}
}
}
- if (next_pf_time != 0)
+ if (next_pf_time != MaxTick)
requestMemSideBus(Request_PF, std::max(time, next_pf_time));
// copy writebacks to write buffer
diff -r 0b969a35781f -r b9646f4546ad src/mem/cache/prefetch/Prefetcher.py
--- a/src/mem/cache/prefetch/Prefetcher.py Tue Dec 23 09:31:18 2014 -0500
+++ b/src/mem/cache/prefetch/Prefetcher.py Tue Dec 23 09:31:18 2014 -0500
@@ -1,4 +1,4 @@
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012, 2014 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -37,6 +37,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Ron Dreslinski
+# Mitch Hayenga
from ClockedObject import ClockedObject
from m5.params import *
@@ -46,39 +47,46 @@
type = 'BasePrefetcher'
abstract = True
cxx_header = "mem/cache/prefetch/base.hh"
- size = Param.Int(100,
- "Number of entries in the hardware prefetch queue")
- cross_pages = Param.Bool(False,
- "Allow prefetches to cross virtual page boundaries")
- serial_squash = Param.Bool(False,
- "Squash prefetches with a later time on a subsequent miss")
- degree = Param.Int(1,
- "Degree of the prefetch depth")
- latency = Param.Cycles('1', "Latency of the prefetcher")
- use_master_id = Param.Bool(True,
- "Use the master id to separate calculations of prefetches")
- data_accesses_only = Param.Bool(False,
- "Only prefetch on data not on instruction accesses")
- on_miss_only = Param.Bool(False,
- "Only prefetch on miss (as opposed to always)")
- on_read_only = Param.Bool(False,
- "Only prefetch on read requests (write requests ignored)")
- on_prefetch = Param.Bool(True,
- "Let lower cache prefetcher train on prefetch requests")
- inst_tagged = Param.Bool(True,
- "Perform a tagged prefetch for instruction fetches always")
sys = Param.System(Parent.any, "System this prefetcher belongs to")
-class StridePrefetcher(BasePrefetcher):
+ on_miss = Param.Bool(False, "Only notify prefetcher on misses")
+ on_read = Param.Bool(True, "Notify prefetcher on reads")
+ on_write = Param.Bool(True, "Notify prefetcher on writes")
+ on_data = Param.Bool(True, "Notify prefetcher on data accesses")
+ on_inst = Param.Bool(True, "Notify prefetcher on instruction accesses")
+
+class QueuedPrefetcher(BasePrefetcher):
+ type = "QueuedPrefetcher"
+ abstract = True
+ cxx_class = "QueuedPrefetcher"
+ cxx_header = "mem/cache/prefetch/queued.hh"
+ latency = Param.Int(1, "Latency for generated prefetches")
+ queue_size = Param.Int(32, "Maximum number of queued prefetches")
+ queue_squash = Param.Bool(True, "Squash queued prefetch on demand access")
+ queue_filter = Param.Bool(True, "Don't queue redundant prefetches")
+ cache_snoop = Param.Bool(False, "Snoop cache to eliminate redundant
request")
+
+ tag_prefetch = Param.Bool(True, "Tag prefetch with PC of generating
access")
+
+class StridePrefetcher(QueuedPrefetcher):
type = 'StridePrefetcher'
cxx_class = 'StridePrefetcher'
cxx_header = "mem/cache/prefetch/stride.hh"
-class TaggedPrefetcher(BasePrefetcher):
+ max_conf = Param.Int(7, "Maximum confidence level")
+ thresh_conf = Param.Int(4, "Threshold confidence level")
+ min_conf = Param.Int(0, "Minimum confidence level")
+ start_conf = Param.Int(4, "Starting confidence for new entries")
+
+ table_sets = Param.Int(16, "Number of sets in PC lookup table")
+ table_assoc = Param.Int(4, "Associativity of PC lookup table")
+ use_master_id = Param.Bool(True, "Use master id based history")
+
+ degree = Param.Int(4, "Number of prefetches to generate")
+
+class TaggedPrefetcher(QueuedPrefetcher):
type = 'TaggedPrefetcher'
cxx_class = 'TaggedPrefetcher'
cxx_header = "mem/cache/prefetch/tagged.hh"
-
-
-
+ degree = Param.Int(2, "Number of prefetches to generate")
diff -r 0b969a35781f -r b9646f4546ad src/mem/cache/prefetch/SConscript
--- a/src/mem/cache/prefetch/SConscript Tue Dec 23 09:31:18 2014 -0500
+++ b/src/mem/cache/prefetch/SConscript Tue Dec 23 09:31:18 2014 -0500
@@ -33,6 +33,7 @@
SimObject('Prefetcher.py')
Source('base.cc')
+Source('queued.cc')
Source('stride.cc')
Source('tagged.cc')
diff -r 0b969a35781f -r b9646f4546ad src/mem/cache/prefetch/base.cc
--- a/src/mem/cache/prefetch/base.cc Tue Dec 23 09:31:18 2014 -0500
+++ b/src/mem/cache/prefetch/base.cc Tue Dec 23 09:31:18 2014 -0500
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013 ARM Limited
+ * Copyright (c) 2013-2014 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -38,6 +38,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Ron Dreslinski
+ * Mitch Hayenga
*/
/**
@@ -47,20 +48,14 @@
#include <list>
-#include "base/trace.hh"
-#include "debug/HWPrefetch.hh"
#include "mem/cache/prefetch/base.hh"
#include "mem/cache/base.hh"
-#include "mem/request.hh"
#include "sim/system.hh"
-BasePrefetcher::BasePrefetcher(const Params *p)
- : ClockedObject(p), size(p->size), cache(nullptr), blkSize(0),
- latency(p->latency), degree(p->degree),
- useMasterId(p->use_master_id), pageStop(!p->cross_pages),
- serialSquash(p->serial_squash), onlyData(p->data_accesses_only),
- onMissOnly(p->on_miss_only), onReadOnly(p->on_read_only),
- onPrefetch(p->on_prefetch), system(p->sys),
+BasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p)
+ : ClockedObject(p), cache(nullptr), blkSize(0), system(p->sys),
+ onMiss(p->on_miss), onRead(p->on_read),
+ onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst),
masterId(system->getMasterId(name())),
pageBytes(system->getPageBytes())
{
@@ -77,239 +72,52 @@
void
BasePrefetcher::regStats()
{
- pfIdentified
- .name(name() + ".prefetcher.num_hwpf_identified")
- .desc("number of hwpf identified")
- ;
-
- pfMSHRHit
- .name(name() + ".prefetcher.num_hwpf_already_in_mshr")
- .desc("number of hwpf that were already in mshr")
- ;
-
- pfCacheHit
- .name(name() + ".prefetcher.num_hwpf_already_in_cache")
- .desc("number of hwpf that were already in the cache")
- ;
-
- pfBufferHit
- .name(name() + ".prefetcher.num_hwpf_already_in_prefetcher")
- .desc("number of hwpf that were already in the prefetch queue")
- ;
-
- pfRemovedFull
- .name(name() + ".prefetcher.num_hwpf_evicted")
- .desc("number of hwpf removed due to no buffer left")
- ;
-
- pfRemovedMSHR
- .name(name() + ".prefetcher.num_hwpf_removed_MSHR_hit")
- .desc("number of hwpf removed because MSHR allocated")
- ;
-
pfIssued
- .name(name() + ".prefetcher.num_hwpf_issued")
+ .name(name() + ".num_hwpf_issued")
.desc("number of hwpf issued")
;
-
- pfSpanPage
- .name(name() + ".prefetcher.num_hwpf_span_page")
- .desc("number of hwpf spanning a virtual page")
- ;
-
- pfSquashed
- .name(name() + ".prefetcher.num_hwpf_squashed_from_miss")
- .desc("number of hwpf that got squashed due to a miss "
- "aborting calculation time")
- ;
}
-inline bool
-BasePrefetcher::inCache(Addr addr, bool is_secure)
+bool
+BasePrefetcher::observeAccess(const PacketPtr &pkt) const
+{
+ Addr addr = pkt->getAddr();
+ bool fetch = pkt->req->isInstFetch();
+ bool read= pkt->isRead();
+ bool is_secure = pkt->isSecure();
+
+ if (pkt->req->isUncacheable()) return false;
+ if (fetch && !onInst) return false;
+ if (!fetch && !onData) return false;
+ if (!fetch && read && !onRead) return false;
+ if (!fetch && !read && !onWrite) return false;
+
+ if (onMiss) {
+ return !inCache(addr, is_secure) &&
+ !inMissQueue(addr, is_secure);
+ }
+
+ return true;
+}
+
+bool
+BasePrefetcher::inCache(Addr addr, bool is_secure) const
{
if (cache->inCache(addr, is_secure)) {
- pfCacheHit++;
return true;
}
return false;
}
-inline bool
-BasePrefetcher::inMissQueue(Addr addr, bool is_secure)
+bool
+BasePrefetcher::inMissQueue(Addr addr, bool is_secure) const
{
if (cache->inMissQueue(addr, is_secure)) {
- pfMSHRHit++;
return true;
}
return false;
}
-PacketPtr
-BasePrefetcher::getPacket()
-{
- DPRINTF(HWPrefetch, "Requesting a hw_pf to issue\n");
-
- if (pf.empty()) {
- DPRINTF(HWPrefetch, "No HW_PF found\n");
- return NULL;
- }
-
- PacketPtr pkt = pf.begin()->pkt;
- while (!pf.empty()) {
- pkt = pf.begin()->pkt;
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