Hi everyone, I have been trying to run with SMT enabled in SE mode, using x86. It seems ZeroRegister gets mapped to index 16 for the first hardware thread, which is also register t0 that is used by the microcode. For the following hardware threads the ZeroRegister will get mapped to 54, 92, 130 and so on, as there are 16 architectural registers and 22 microcode and additional registers which leads to 38 total registers per hardware thread. All these registers are renamed and because of all this the following assert(prev_reg == zeroReg) fails in SimpleRenameMap::rename.
Mapping the ZeroReg to some huge index into the register file introduces new issues as t0 is not maintained 0 any more and effective address computations which include t0 will be wrong. On the other hand if the rename logic is modified to keep the initial mapping to the physical register file for register index 16 of all hardware threads (mapped to 16, 54, 92 etc.) the program counter gets corrupted to 0 and a fault is produced as it tries to execute from address 0. >From the observed behavior it seems that register t0 needs to play the role of >a zero register with the current microcode implementation. Can somebody please >comment if this is required? Thank you, Alex _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
