changeset 829adc48e175 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=829adc48e175 description: arch: Make readMiscRegNoEffect const throughout
Finally took the plunge and made this apply to all ISAs, not just ARM. diffstat: src/arch/alpha/isa.cc | 2 +- src/arch/alpha/isa.hh | 2 +- src/arch/mips/isa.cc | 4 ++-- src/arch/mips/isa.hh | 4 ++-- src/arch/power/isa.hh | 2 +- src/arch/sparc/isa.cc | 2 +- src/arch/sparc/isa.hh | 2 +- src/arch/x86/isa.cc | 2 +- src/arch/x86/isa.hh | 2 +- src/cpu/checker/cpu.hh | 2 +- src/cpu/checker/thread_context.hh | 2 +- src/cpu/minor/exec_context.hh | 2 +- src/cpu/o3/cpu.cc | 2 +- src/cpu/o3/cpu.hh | 2 +- src/cpu/o3/thread_context.hh | 2 +- src/cpu/simple/base.hh | 2 +- src/cpu/simple_thread.hh | 2 +- src/cpu/thread_context.hh | 4 ++-- 18 files changed, 21 insertions(+), 21 deletions(-) diffs (242 lines): diff -r 71c40e5c8bd4 -r 829adc48e175 src/arch/alpha/isa.cc --- a/src/arch/alpha/isa.cc Fri Jan 16 14:12:03 2015 -0600 +++ b/src/arch/alpha/isa.cc Mon Feb 16 03:33:28 2015 -0500 @@ -74,7 +74,7 @@ MiscReg -ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) +ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const { switch (misc_reg) { case MISCREG_FPCR: diff -r 71c40e5c8bd4 -r 829adc48e175 src/arch/alpha/isa.hh --- a/src/arch/alpha/isa.hh Fri Jan 16 14:12:03 2015 -0600 +++ b/src/arch/alpha/isa.hh Mon Feb 16 03:33:28 2015 -0500 @@ -73,7 +73,7 @@ public: - MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0); + MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const; MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0); void setMiscRegNoEffect(int misc_reg, const MiscReg &val, diff -r 71c40e5c8bd4 -r 829adc48e175 src/arch/mips/isa.cc --- a/src/arch/mips/isa.cc Fri Jan 16 14:12:03 2015 -0600 +++ b/src/arch/mips/isa.cc Mon Feb 16 03:33:28 2015 -0500 @@ -410,14 +410,14 @@ } inline unsigned -ISA::getVPENum(ThreadID tid) +ISA::getVPENum(ThreadID tid) const { TCBindReg tcBind = miscRegFile[MISCREG_TC_BIND][tid]; return tcBind.curVPE; } MiscReg -ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) +ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const { unsigned reg_sel = (bankType[misc_reg] == perThreadContext) ? tid : getVPENum(tid); diff -r 71c40e5c8bd4 -r 829adc48e175 src/arch/mips/isa.hh --- a/src/arch/mips/isa.hh Fri Jan 16 14:12:03 2015 -0600 +++ b/src/arch/mips/isa.hh Mon Feb 16 03:33:28 2015 -0500 @@ -76,7 +76,7 @@ void configCP(); - unsigned getVPENum(ThreadID tid); + unsigned getVPENum(ThreadID tid) const; ////////////////////////////////////////////////////////// // @@ -87,7 +87,7 @@ //@TODO: MIPS MT's register view automatically connects // Status to TCStatus depending on current thread void updateCP0ReadView(int misc_reg, ThreadID tid) { } - MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0); + MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const; //template <class TC> MiscReg readMiscReg(int misc_reg, diff -r 71c40e5c8bd4 -r 829adc48e175 src/arch/power/isa.hh --- a/src/arch/power/isa.hh Fri Jan 16 14:12:03 2015 -0600 +++ b/src/arch/power/isa.hh Mon Feb 16 03:33:28 2015 -0500 @@ -61,7 +61,7 @@ } MiscReg - readMiscRegNoEffect(int misc_reg) + readMiscRegNoEffect(int misc_reg) const { fatal("Power does not currently have any misc regs defined\n"); return dummy; diff -r 71c40e5c8bd4 -r 829adc48e175 src/arch/sparc/isa.cc --- a/src/arch/sparc/isa.cc Fri Jan 16 14:12:03 2015 -0600 +++ b/src/arch/sparc/isa.cc Mon Feb 16 03:33:28 2015 -0500 @@ -173,7 +173,7 @@ } MiscReg -ISA::readMiscRegNoEffect(int miscReg) +ISA::readMiscRegNoEffect(int miscReg) const { // The three miscRegs are moved up from the switch statement diff -r 71c40e5c8bd4 -r 829adc48e175 src/arch/sparc/isa.hh --- a/src/arch/sparc/isa.hh Fri Jan 16 14:12:03 2015 -0600 +++ b/src/arch/sparc/isa.hh Mon Feb 16 03:33:28 2015 -0500 @@ -183,7 +183,7 @@ public: - MiscReg readMiscRegNoEffect(int miscReg); + MiscReg readMiscRegNoEffect(int miscReg) const; MiscReg readMiscReg(int miscReg, ThreadContext *tc); void setMiscRegNoEffect(int miscReg, const MiscReg val); diff -r 71c40e5c8bd4 -r 829adc48e175 src/arch/x86/isa.cc --- a/src/arch/x86/isa.cc Fri Jan 16 14:12:03 2015 -0600 +++ b/src/arch/x86/isa.cc Mon Feb 16 03:33:28 2015 -0500 @@ -124,7 +124,7 @@ } MiscReg -ISA::readMiscRegNoEffect(int miscReg) +ISA::readMiscRegNoEffect(int miscReg) const { // Make sure we're not dealing with an illegal control register. // Instructions should filter out these indexes, and nothing else should diff -r 71c40e5c8bd4 -r 829adc48e175 src/arch/x86/isa.hh --- a/src/arch/x86/isa.hh Fri Jan 16 14:12:03 2015 -0600 +++ b/src/arch/x86/isa.hh Mon Feb 16 03:33:28 2015 -0500 @@ -63,7 +63,7 @@ ISA(Params *p); const Params *params() const; - MiscReg readMiscRegNoEffect(int miscReg); + MiscReg readMiscRegNoEffect(int miscReg) const; MiscReg readMiscReg(int miscReg, ThreadContext *tc); void setMiscRegNoEffect(int miscReg, MiscReg val); diff -r 71c40e5c8bd4 -r 829adc48e175 src/cpu/checker/cpu.hh --- a/src/cpu/checker/cpu.hh Fri Jan 16 14:12:03 2015 -0600 +++ b/src/cpu/checker/cpu.hh Mon Feb 16 03:33:28 2015 -0500 @@ -285,7 +285,7 @@ MicroPC microPC() { return thread->microPC(); } ////////////////////////////////////////// - MiscReg readMiscRegNoEffect(int misc_reg) + MiscReg readMiscRegNoEffect(int misc_reg) const { return thread->readMiscRegNoEffect(misc_reg); } diff -r 71c40e5c8bd4 -r 829adc48e175 src/cpu/checker/thread_context.hh --- a/src/cpu/checker/thread_context.hh Fri Jan 16 14:12:03 2015 -0600 +++ b/src/cpu/checker/thread_context.hh Mon Feb 16 03:33:28 2015 -0500 @@ -275,7 +275,7 @@ MicroPC microPC() { return actualTC->microPC(); } - MiscReg readMiscRegNoEffect(int misc_reg) + MiscReg readMiscRegNoEffect(int misc_reg) const { return actualTC->readMiscRegNoEffect(misc_reg); } MiscReg readMiscReg(int misc_reg) diff -r 71c40e5c8bd4 -r 829adc48e175 src/cpu/minor/exec_context.hh --- a/src/cpu/minor/exec_context.hh Fri Jan 16 14:12:03 2015 -0600 +++ b/src/cpu/minor/exec_context.hh Mon Feb 16 03:33:28 2015 -0500 @@ -187,7 +187,7 @@ } TheISA::MiscReg - readMiscRegNoEffect(int misc_reg) + readMiscRegNoEffect(int misc_reg) const { return thread.readMiscRegNoEffect(misc_reg); } diff -r 71c40e5c8bd4 -r 829adc48e175 src/cpu/o3/cpu.cc --- a/src/cpu/o3/cpu.cc Fri Jan 16 14:12:03 2015 -0600 +++ b/src/cpu/o3/cpu.cc Mon Feb 16 03:33:28 2015 -0500 @@ -1205,7 +1205,7 @@ template <class Impl> TheISA::MiscReg -FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) +FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const { return this->isa[tid]->readMiscRegNoEffect(misc_reg); } diff -r 71c40e5c8bd4 -r 829adc48e175 src/cpu/o3/cpu.hh --- a/src/cpu/o3/cpu.hh Fri Jan 16 14:12:03 2015 -0600 +++ b/src/cpu/o3/cpu.hh Mon Feb 16 03:33:28 2015 -0500 @@ -403,7 +403,7 @@ /** Register accessors. Index refers to the physical register index. */ /** Reads a miscellaneous register. */ - TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid); + TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid) const; /** Reads a misc. register, including any side effects the read * might have as defined by the architecture. diff -r 71c40e5c8bd4 -r 829adc48e175 src/cpu/o3/thread_context.hh --- a/src/cpu/o3/thread_context.hh Fri Jan 16 14:12:03 2015 -0600 +++ b/src/cpu/o3/thread_context.hh Mon Feb 16 03:33:28 2015 -0500 @@ -228,7 +228,7 @@ { return cpu->microPC(thread->threadId()); } /** Reads a miscellaneous register. */ - virtual MiscReg readMiscRegNoEffect(int misc_reg) + virtual MiscReg readMiscRegNoEffect(int misc_reg) const { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); } /** Reads a misc. register, including any side-effects the diff -r 71c40e5c8bd4 -r 829adc48e175 src/cpu/simple/base.hh --- a/src/cpu/simple/base.hh Fri Jan 16 14:12:03 2015 -0600 +++ b/src/cpu/simple/base.hh Mon Feb 16 03:33:28 2015 -0500 @@ -367,7 +367,7 @@ Addr nextInstAddr() { return thread->nextInstAddr(); } MicroPC microPC() { return thread->microPC(); } - MiscReg readMiscRegNoEffect(int misc_reg) + MiscReg readMiscRegNoEffect(int misc_reg) const { return thread->readMiscRegNoEffect(misc_reg); } diff -r 71c40e5c8bd4 -r 829adc48e175 src/cpu/simple_thread.hh --- a/src/cpu/simple_thread.hh Fri Jan 16 14:12:03 2015 -0600 +++ b/src/cpu/simple_thread.hh Mon Feb 16 03:33:28 2015 -0500 @@ -372,7 +372,7 @@ } MiscReg - readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) + readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const { return isa->readMiscRegNoEffect(misc_reg); } diff -r 71c40e5c8bd4 -r 829adc48e175 src/cpu/thread_context.hh --- a/src/cpu/thread_context.hh Fri Jan 16 14:12:03 2015 -0600 +++ b/src/cpu/thread_context.hh Mon Feb 16 03:33:28 2015 -0500 @@ -225,7 +225,7 @@ virtual MicroPC microPC() = 0; - virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; + virtual MiscReg readMiscRegNoEffect(int misc_reg) const = 0; virtual MiscReg readMiscReg(int misc_reg) = 0; @@ -429,7 +429,7 @@ void setPredicate(bool val) { actualTC->setPredicate(val); } - MiscReg readMiscRegNoEffect(int misc_reg) + MiscReg readMiscRegNoEffect(int misc_reg) const { return actualTC->readMiscRegNoEffect(misc_reg); } MiscReg readMiscReg(int misc_reg) _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev