changeset b5e5068fcb26 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b5e5068fcb26
description:
arm: Merge ISA files with pseudo instructions
This changeset moves the pseudo instructions used to signal unknown
instructions and unimplemented instructions to the same source files
as the decoder fault.
diffstat:
src/arch/arm/insts/pseudo.cc | 101 ++++++++++++++++
src/arch/arm/insts/pseudo.hh | 70 +++++++++++
src/arch/arm/isa/formats/formats.isa | 6 -
src/arch/arm/isa/formats/pseudo.isa | 34 +++++
src/arch/arm/isa/formats/unimp.isa | 215 -----------------------------------
src/arch/arm/isa/formats/unknown.isa | 46 -------
6 files changed, 205 insertions(+), 267 deletions(-)
diffs (truncated from 554 to 300 lines):
diff -r ef2c71a5f02e -r b5e5068fcb26 src/arch/arm/insts/pseudo.cc
--- a/src/arch/arm/insts/pseudo.cc Mon Feb 16 03:32:38 2015 -0500
+++ b/src/arch/arm/insts/pseudo.cc Mon Feb 16 03:32:58 2015 -0500
@@ -11,6 +11,9 @@
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
+ * Copyright (c) 2007-2008 The Florida State University
+ * All rights reserved.
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
@@ -35,6 +38,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Andreas Sandberg
+ * Stephen Hines
*/
#include "arch/arm/insts/pseudo.hh"
@@ -99,3 +103,100 @@
{
return csprintf("gem5fault %s", faultName());
}
+
+
+
+FailUnimplemented::FailUnimplemented(const char *_mnemonic,
+ ExtMachInst _machInst)
+ : ArmStaticInst(_mnemonic, _machInst, No_OpClass)
+{
+ // don't call execute() (which panics) if we're on a
+ // speculative path
+ flags[IsNonSpeculative] = true;
+}
+
+FailUnimplemented::FailUnimplemented(const char *_mnemonic,
+ ExtMachInst _machInst,
+ const std::string& _fullMnemonic)
+ : ArmStaticInst(_mnemonic, _machInst, No_OpClass),
+ fullMnemonic(_fullMnemonic)
+{
+ // don't call execute() (which panics) if we're on a
+ // speculative path
+ flags[IsNonSpeculative] = true;
+}
+
+Fault
+FailUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const
+{
+ return std::make_shared<UndefinedInstruction>(machInst, false, mnemonic);
+}
+
+std::string
+FailUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab)
const
+{
+ return csprintf("%-10s (unimplemented)",
+ fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
+}
+
+
+
+WarnUnimplemented::WarnUnimplemented(const char *_mnemonic,
+ ExtMachInst _machInst)
+ : ArmStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
+{
+ // don't call execute() (which panics) if we're on a
+ // speculative path
+ flags[IsNonSpeculative] = true;
+}
+
+WarnUnimplemented::WarnUnimplemented(const char *_mnemonic,
+ ExtMachInst _machInst,
+ const std::string& _fullMnemonic)
+ : ArmStaticInst(_mnemonic, _machInst, No_OpClass), warned(false),
+ fullMnemonic(_fullMnemonic)
+{
+ // don't call execute() (which panics) if we're on a
+ // speculative path
+ flags[IsNonSpeculative] = true;
+}
+
+Fault
+WarnUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const
+{
+ if (!warned) {
+ warn("\tinstruction '%s' unimplemented\n",
+ fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
+ warned = true;
+ }
+
+ return NoFault;
+}
+
+std::string
+WarnUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab)
const
+{
+ return csprintf("%-10s (unimplemented)",
+ fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
+}
+
+
+
+FlushPipeInst::FlushPipeInst(const char *_mnemonic, ExtMachInst _machInst)
+ : ArmStaticInst(_mnemonic, _machInst, No_OpClass)
+{
+ flags[IsNonSpeculative] = true;
+}
+
+Fault
+FlushPipeInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const
+{
+ Fault fault = std::make_shared<FlushPipe>();
+ return fault;
+}
+
+std::string
+FlushPipeInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ return csprintf("%-10s (pipe flush)", mnemonic);
+}
diff -r ef2c71a5f02e -r b5e5068fcb26 src/arch/arm/insts/pseudo.hh
--- a/src/arch/arm/insts/pseudo.hh Mon Feb 16 03:32:38 2015 -0500
+++ b/src/arch/arm/insts/pseudo.hh Mon Feb 16 03:32:58 2015 -0500
@@ -11,6 +11,9 @@
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
+ * Copyright (c) 2007-2008 The Florida State University
+ * All rights reserved.
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
@@ -35,6 +38,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Andreas Sandberg
+ * Stephen Hines
*/
#ifndef __ARCH_ARM_INSTS_PSEUDO_HH__
@@ -57,5 +61,71 @@
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
+/**
+ * Static instruction class for unimplemented instructions that
+ * cause simulator termination. Note that these are recognized
+ * (legal) instructions that the simulator does not support; the
+ * 'Unknown' class is used for unrecognized/illegal instructions.
+ * This is a leaf class.
+ */
+class FailUnimplemented : public ArmStaticInst
+{
+ private:
+ /// Full mnemonic for MRC and MCR instructions including the
+ /// coproc. register name
+ std::string fullMnemonic;
+
+ public:
+ FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst);
+ FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst,
+ const std::string& _fullMnemonic);
+
+ Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+/**
+ * Base class for unimplemented instructions that cause a warning
+ * to be printed (but do not terminate simulation). This
+ * implementation is a little screwy in that it will print a
+ * warning for each instance of a particular unimplemented machine
+ * instruction, not just for each unimplemented opcode. Should
+ * probably make the 'warned' flag a static member of the derived
+ * class.
+ */
+class WarnUnimplemented : public ArmStaticInst
+{
+ private:
+ /// Have we warned on this instruction yet?
+ mutable bool warned;
+ /// Full mnemonic for MRC and MCR instructions including the
+ /// coproc. register name
+ std::string fullMnemonic;
+
+ public:
+ WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst);
+ WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst,
+ const std::string& _fullMnemonic);
+
+ Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+class FlushPipeInst : public ArmStaticInst
+{
+ public:
+ FlushPipeInst(const char *_mnemonic, ExtMachInst _machInst);
+
+ Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+
+};
+
#endif
diff -r ef2c71a5f02e -r b5e5068fcb26 src/arch/arm/isa/formats/formats.isa
--- a/src/arch/arm/isa/formats/formats.isa Mon Feb 16 03:32:38 2015 -0500
+++ b/src/arch/arm/isa/formats/formats.isa Mon Feb 16 03:32:58 2015 -0500
@@ -68,12 +68,6 @@
//Miscellaneous instructions that don't fit elsewhere
##include "misc.isa"
-//Include the unimplemented format
-##include "unimp.isa"
-
-//Include the unknown format
-##include "unknown.isa"
-
//Include the breakpoint format
##include "breakpoint.isa"
diff -r ef2c71a5f02e -r b5e5068fcb26 src/arch/arm/isa/formats/pseudo.isa
--- a/src/arch/arm/isa/formats/pseudo.isa Mon Feb 16 03:32:38 2015 -0500
+++ b/src/arch/arm/isa/formats/pseudo.isa Mon Feb 16 03:32:58 2015 -0500
@@ -12,6 +12,9 @@
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
+// Copyright (c) 2007-2008 The Florida State University
+// All rights reserved.
+//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
@@ -36,9 +39,40 @@
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Andreas Sandberg
+// Stephen Hines
+
+
+////////////////////////////////////////////////////////////////////
+//
+// Internal fault handling
+//
def format DecoderFault() {{
decode_block = '''
return new DecoderFaultInst(machInst);
'''
}};
+
+////////////////////////////////////////////////////////////////////
+//
+// Unknown instruction handling
+//
+
+def format Unknown() {{
+ decode_block = 'return new Unknown(machInst);\n'
+}};
+
+////////////////////////////////////////////////////////////////////
+//
+// Unimplemented instructions
+//
+
+def format FailUnimpl() {{
+ iop = InstObjParams(name, 'FailUnimplemented')
+ decode_block = BasicDecodeWithMnemonic.subst(iop)
+}};
+
+def format WarnUnimpl() {{
+ iop = InstObjParams(name, 'WarnUnimplemented')
+ decode_block = BasicDecodeWithMnemonic.subst(iop)
+}};
diff -r ef2c71a5f02e -r b5e5068fcb26 src/arch/arm/isa/formats/unimp.isa
--- a/src/arch/arm/isa/formats/unimp.isa Mon Feb 16 03:32:38 2015 -0500
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,215 +0,0 @@
-// -*- mode:c++ -*-
-
-// Copyright (c) 2010, 2012 ARM Limited
-// All rights reserved
-//
-// The license below extends only to copyright in the software and shall
-// not be construed as granting a license to any other intellectual
-// property including but not limited to intellectual property relating
-// to a hardware implementation of the functionality of the software
-// licensed hereunder. You may use the software subject to the license
-// terms below provided that you ensure that this notice is replicated
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