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Review request for Default. Repository: gem5 Description ------- Changeset 10708:344bc6b7203d --------------------------- ext: Add SST connector This patch adds a connector that allows gem5 to be used as a component in SST (Structural Simulation Toolkit, sst-simulator.org). At a high level, this allows memory traffic to pass between the two simulators. SST Links are roughly analogous to gem5 Ports, although Links do not have a notion of master and slave. This distinction is important to gem5, so when connecting a gem5 CPU to an SST cache, an ExternalSlave must be used, and similarly when connecting the memory side of SST cache to a gem5 port (for memory <-> I/O), an ExternalMaster must be used. These connectors handle the administrative aspects of gem5 (initialization, simulation, shutdown) as well as translating SST's MemEvents into gem5 Packets and vice-versa. Diffs ----- ext/sst/ExtMaster.hh PRE-CREATION ext/sst/ExtMaster.cc PRE-CREATION ext/sst/ExtSlave.hh PRE-CREATION ext/sst/ExtSlave.cc PRE-CREATION ext/sst/LICENSE PRE-CREATION ext/sst/Makefile PRE-CREATION ext/sst/README PRE-CREATION ext/sst/gem5.hh PRE-CREATION ext/sst/gem5.cc PRE-CREATION ext/sst/libgem5.cc PRE-CREATION Diff: http://reviews.gem5.org/r/2667/diff/ Testing ------- Thanks, Curtis Dunham _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
