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OK.  I am sorry for not realizing that so many changes would be required to 
separate out
the params just meant for LTAGE.  Had I had realized that, I probably would not 
have asked for it.
I think we should break this latest version into two separate patches.  The 
first patch
creates these separate sim objects for different predictor types. The second 
patch adds LTAGE.

And I am willing to go with either order between those two patches.  That is, 
if you prefer, you
can add LTAGE first and then separate out the predictors.

- Nilay Vaish


On March 4, 2015, 5:52 p.m., Dibakar Gope wrote:
> 
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> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/2619/
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> 
> (Updated March 4, 2015, 5:52 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> -------
> 
> It is the L-TAGE predictor from the Branch Prediction Championship, 
> originally coded by Vignyan Reddy, and modified by me.
> 
> 
> Diffs
> -----
> 
>   configs/common/O3_ARM_v7a.py 8a20e2a1562d 
>   src/cpu/inorder/InOrderCPU.py 8a20e2a1562d 
>   src/cpu/minor/MinorCPU.py 8a20e2a1562d 
>   src/cpu/o3/O3CPU.py 8a20e2a1562d 
>   src/cpu/pred/2bit_local.hh 8a20e2a1562d 
>   src/cpu/pred/2bit_local.cc 8a20e2a1562d 
>   src/cpu/pred/BranchPredictor.py 8a20e2a1562d 
>   src/cpu/pred/SConscript 8a20e2a1562d 
>   src/cpu/pred/bi_mode.hh 8a20e2a1562d 
>   src/cpu/pred/bi_mode.cc 8a20e2a1562d 
>   src/cpu/pred/bpred_unit.hh 8a20e2a1562d 
>   src/cpu/pred/bpred_unit.cc 8a20e2a1562d 
>   src/cpu/pred/bpred_unit_impl.hh 8a20e2a1562d 
>   src/cpu/pred/ltage.hh PRE-CREATION 
>   src/cpu/pred/ltage.cc PRE-CREATION 
>   src/cpu/pred/tournament.hh 8a20e2a1562d 
>   src/cpu/pred/tournament.cc 8a20e2a1562d 
>   src/cpu/simple/BaseSimpleCPU.py 8a20e2a1562d 
> 
> Diff: http://reviews.gem5.org/r/2619/diff/
> 
> 
> Testing
> -------
> 
> 
> Thanks,
> 
> Dibakar Gope
> 
>

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