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Review request for Default. Repository: gem5 Description ------- Changeset 10860:f4565ce598dd --------------------------- x86, o3: Enabling x86 TLBs for multiple hardware threads This patch extends the x86 TLB to be shared among multiple hardware threads. Its size will represent the number of all TLB entries that can be allocated to all threads, therefore there is statically assigned number of entries per thread. Diffs ----- src/arch/generic/tlb.hh d02b45a554b52c68cce41e1b3895fb8582a639dd src/arch/x86/isa.cc d02b45a554b52c68cce41e1b3895fb8582a639dd src/arch/x86/pagetable.hh d02b45a554b52c68cce41e1b3895fb8582a639dd src/arch/x86/pagetable.cc d02b45a554b52c68cce41e1b3895fb8582a639dd src/arch/x86/pagetable_walker.cc d02b45a554b52c68cce41e1b3895fb8582a639dd src/arch/x86/tlb.hh d02b45a554b52c68cce41e1b3895fb8582a639dd src/arch/x86/tlb.cc d02b45a554b52c68cce41e1b3895fb8582a639dd src/cpu/o3/cpu.cc d02b45a554b52c68cce41e1b3895fb8582a639dd Diff: http://reviews.gem5.org/r/2853/diff/ Testing ------- Quick regressions passed for all ISAs. Thanks, Alexandru Dutu _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
