changeset b99a6662d7c2 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b99a6662d7c2
description:
sim: Decouple draining from the SimObject hierarchy
Draining is currently done by traversing the SimObject graph and
calling drain()/drainResume() on the SimObjects. This is not ideal
when non-SimObjects (e.g., ports) need draining since this means that
SimObjects owning those objects need to be aware of this.
This changeset moves the responsibility for finding objects that need
draining from SimObjects and the Python-side of the simulator to the
DrainManager. The DrainManager now maintains a set of all objects that
need draining. To reduce the overhead in classes owning non-SimObjects
that need draining, objects inheriting from Drainable now
automatically register with the DrainManager. If such an object is
destroyed, it is automatically unregistered. This means that drain()
and drainResume() should never be called directly on a Drainable
object.
While implementing the new functionality, the DrainManager has now
been made thread safe. In practice, this means that it takes a lock
whenever it manipulates the set of Drainable objects since SimObjects
in different threads may create Drainable objects
dynamically. Similarly, the drain counter is now an atomic_uint, which
ensures that it is manipulated correctly when objects signal that they
are done draining.
A nice side effect of these changes is that it makes the drain state
changes stricter, which the simulation scripts can exploit to avoid
redundant drains.
diffstat:
src/arch/arm/stage2_mmu.cc | 6 -
src/arch/arm/stage2_mmu.hh | 2 -
src/dev/arm/ufs_device.cc | 14 +---
src/dev/copy_engine.cc | 30 +--------
src/dev/copy_engine.hh | 3 -
src/dev/dma_device.cc | 11 ---
src/dev/dma_device.hh | 4 +-
src/dev/i8254xGBe.cc | 3 +-
src/dev/io_device.cc | 12 ---
src/dev/io_device.hh | 2 -
src/dev/pcidev.cc | 12 ---
src/dev/pcidev.hh | 2 -
src/mem/cache/base.cc | 17 ----
src/mem/cache/base.hh | 2 -
src/mem/coherent_xbar.cc | 14 ----
src/mem/coherent_xbar.hh | 2 -
src/mem/dram_ctrl.cc | 14 +--
src/mem/noncoherent_xbar.cc | 12 ---
src/mem/noncoherent_xbar.hh | 2 -
src/mem/qport.hh | 5 -
src/mem/ruby/system/DMASequencer.cc | 18 +----
src/mem/ruby/system/RubyPort.cc | 35 +---------
src/mem/ruby/system/RubyPort.hh | 2 -
src/mem/xbar.hh | 2 -
src/python/m5/simulate.py | 83 ++++++++++-------------
src/python/swig/drain.i | 18 -----
src/sim/cxx_manager.cc | 11 +--
src/sim/cxx_manager.hh | 2 +-
src/sim/drain.cc | 104 ++++++++++++++++++++++++++++-
src/sim/drain.hh | 126 ++++++++++++++++++++++++-----------
tests/configs/switcheroo.py | 5 +-
31 files changed, 243 insertions(+), 332 deletions(-)
diffs (truncated from 1139 to 300 lines):
diff -r 0ca18446a5bb -r b99a6662d7c2 src/arch/arm/stage2_mmu.cc
--- a/src/arch/arm/stage2_mmu.cc Tue Jul 07 09:51:04 2015 +0100
+++ b/src/arch/arm/stage2_mmu.cc Tue Jul 07 09:51:05 2015 +0100
@@ -141,12 +141,6 @@
}
}
-unsigned int
-Stage2MMU::drain(DrainManager *dm)
-{
- return port.drain(dm);
-}
-
ArmISA::Stage2MMU *
ArmStage2MMUParams::create()
{
diff -r 0ca18446a5bb -r b99a6662d7c2 src/arch/arm/stage2_mmu.hh
--- a/src/arch/arm/stage2_mmu.hh Tue Jul 07 09:51:04 2015 +0100
+++ b/src/arch/arm/stage2_mmu.hh Tue Jul 07 09:51:05 2015 +0100
@@ -112,8 +112,6 @@
*/
DmaPort& getPort() { return port; }
- unsigned int drain(DrainManager *dm);
-
Fault readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
uint8_t *data, int numBytes, Request::Flags flags, bool isFunctional);
Fault readDataTimed(ThreadContext *tc, Addr descAddr,
diff -r 0ca18446a5bb -r b99a6662d7c2 src/dev/arm/ufs_device.cc
--- a/src/dev/arm/ufs_device.cc Tue Jul 07 09:51:04 2015 +0100
+++ b/src/dev/arm/ufs_device.cc Tue Jul 07 09:51:05 2015 +0100
@@ -2319,26 +2319,16 @@
unsigned int
UFSHostDevice::drain(DrainManager *dm)
{
- unsigned int count = 0;
-
- // check pio, dma port, and doorbells
- count = pioPort.drain(dm) + dmaPort.drain(dm);
-
if (UFSHCIMem.TRUTRLDBR) {
- count += 1;
drainManager = dm;
- } else {
- DPRINTF(UFSHostDevice, "UFSHostDevice in drained state\n");
- }
-
- if (count) {
DPRINTF(UFSHostDevice, "UFSDevice is draining...\n");
setDrainState(DrainState::Draining);
+ return 1;
} else {
DPRINTF(UFSHostDevice, "UFSDevice drained\n");
setDrainState(DrainState::Drained);
+ return 0;
}
- return count;
}
/**
diff -r 0ca18446a5bb -r b99a6662d7c2 src/dev/copy_engine.cc
--- a/src/dev/copy_engine.cc Tue Jul 07 09:51:04 2015 +0100
+++ b/src/dev/copy_engine.cc Tue Jul 07 09:51:05 2015 +0100
@@ -650,29 +650,10 @@
{
if (nextState == Idle || ce->getDrainState() != DrainState::Running)
return 0;
- unsigned int count = 1;
- count += cePort.drain(dm);
DPRINTF(Drain, "CopyEngineChannel not drained\n");
this->drainManager = dm;
- return count;
-}
-
-unsigned int
-CopyEngine::drain(DrainManager *dm)
-{
- unsigned int count;
- count = pioPort.drain(dm) + dmaPort.drain(dm) + configPort.drain(dm);
- for (int x = 0;x < chan.size(); x++)
- count += chan[x]->drain(dm);
-
- if (count)
- setDrainState(DrainState::Draining);
- else
- setDrainState(DrainState::Drained);
-
- DPRINTF(Drain, "CopyEngine not drained\n");
- return count;
+ return 1;
}
void
@@ -756,15 +737,6 @@
}
void
-CopyEngine::drainResume()
-{
- Drainable::drainResume();
- for (int x = 0;x < chan.size(); x++)
- chan[x]->drainResume();
-}
-
-
-void
CopyEngine::CopyEngineChannel::drainResume()
{
DPRINTF(DMACopyEngine, "Restarting state machine at state %d\n",
nextState);
diff -r 0ca18446a5bb -r b99a6662d7c2 src/dev/copy_engine.hh
--- a/src/dev/copy_engine.hh Tue Jul 07 09:51:04 2015 +0100
+++ b/src/dev/copy_engine.hh Tue Jul 07 09:51:05 2015 +0100
@@ -207,9 +207,6 @@
void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
-
- unsigned int drain(DrainManager *drainManger);
- void drainResume();
};
#endif //__DEV_COPY_ENGINE_HH__
diff -r 0ca18446a5bb -r b99a6662d7c2 src/dev/dma_device.cc
--- a/src/dev/dma_device.cc Tue Jul 07 09:51:04 2015 +0100
+++ b/src/dev/dma_device.cc Tue Jul 07 09:51:05 2015 +0100
@@ -126,17 +126,6 @@
}
unsigned int
-DmaDevice::drain(DrainManager *dm)
-{
- unsigned int count = pioPort.drain(dm) + dmaPort.drain(dm);
- if (count)
- setDrainState(DrainState::Draining);
- else
- setDrainState(DrainState::Drained);
- return count;
-}
-
-unsigned int
DmaPort::drain(DrainManager *dm)
{
if (pendingCount == 0)
diff -r 0ca18446a5bb -r b99a6662d7c2 src/dev/dma_device.hh
--- a/src/dev/dma_device.hh Tue Jul 07 09:51:04 2015 +0100
+++ b/src/dev/dma_device.hh Tue Jul 07 09:51:05 2015 +0100
@@ -51,7 +51,7 @@
#include "sim/drain.hh"
#include "sim/system.hh"
-class DmaPort : public MasterPort
+class DmaPort : public MasterPort, public Drainable
{
private:
@@ -176,8 +176,6 @@
virtual void init();
- unsigned int drain(DrainManager *drainManger);
-
unsigned int cacheBlockSize() const { return sys->cacheLineSize(); }
virtual BaseMasterPort &getMasterPort(const std::string &if_name,
diff -r 0ca18446a5bb -r b99a6662d7c2 src/dev/i8254xGBe.cc
--- a/src/dev/i8254xGBe.cc Tue Jul 07 09:51:04 2015 +0100
+++ b/src/dev/i8254xGBe.cc Tue Jul 07 09:51:05 2015 +0100
@@ -2058,8 +2058,7 @@
unsigned int
IGbE::drain(DrainManager *dm)
{
- unsigned int count;
- count = pioPort.drain(dm) + dmaPort.drain(dm);
+ unsigned int count(0);
if (rxDescCache.hasOutstandingEvents() ||
txDescCache.hasOutstandingEvents()) {
count++;
diff -r 0ca18446a5bb -r b99a6662d7c2 src/dev/io_device.cc
--- a/src/dev/io_device.cc Tue Jul 07 09:51:04 2015 +0100
+++ b/src/dev/io_device.cc Tue Jul 07 09:51:05 2015 +0100
@@ -93,18 +93,6 @@
return MemObject::getSlavePort(if_name, idx);
}
-unsigned int
-PioDevice::drain(DrainManager *dm)
-{
- unsigned int count;
- count = pioPort.drain(dm);
- if (count)
- setDrainState(DrainState::Draining);
- else
- setDrainState(DrainState::Drained);
- return count;
-}
-
BasicPioDevice::BasicPioDevice(const Params *p, Addr size)
: PioDevice(p), pioAddr(p->pio_addr), pioSize(size),
pioDelay(p->pio_latency)
diff -r 0ca18446a5bb -r b99a6662d7c2 src/dev/io_device.hh
--- a/src/dev/io_device.hh Tue Jul 07 09:51:04 2015 +0100
+++ b/src/dev/io_device.hh Tue Jul 07 09:51:05 2015 +0100
@@ -125,8 +125,6 @@
virtual void init();
- unsigned int drain(DrainManager *drainManger);
-
virtual BaseSlavePort &getSlavePort(const std::string &if_name,
PortID idx = InvalidPortID);
diff -r 0ca18446a5bb -r b99a6662d7c2 src/dev/pcidev.cc
--- a/src/dev/pcidev.cc Tue Jul 07 09:51:04 2015 +0100
+++ b/src/dev/pcidev.cc Tue Jul 07 09:51:05 2015 +0100
@@ -255,18 +255,6 @@
DmaDevice::init();
}
-unsigned int
-PciDevice::drain(DrainManager *dm)
-{
- unsigned int count;
- count = pioPort.drain(dm) + dmaPort.drain(dm) + configPort.drain(dm);
- if (count)
- setDrainState(DrainState::Draining);
- else
- setDrainState(DrainState::Drained);
- return count;
-}
-
Tick
PciDevice::readConfig(PacketPtr pkt)
{
diff -r 0ca18446a5bb -r b99a6662d7c2 src/dev/pcidev.hh
--- a/src/dev/pcidev.hh Tue Jul 07 09:51:04 2015 +0100
+++ b/src/dev/pcidev.hh Tue Jul 07 09:51:05 2015 +0100
@@ -259,8 +259,6 @@
void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
- virtual unsigned int drain(DrainManager *dm);
-
virtual BaseSlavePort &getSlavePort(const std::string &if_name,
PortID idx = InvalidPortID)
{
diff -r 0ca18446a5bb -r b99a6662d7c2 src/mem/cache/base.cc
--- a/src/mem/cache/base.cc Tue Jul 07 09:51:04 2015 +0100
+++ b/src/mem/cache/base.cc Tue Jul 07 09:51:05 2015 +0100
@@ -775,23 +775,6 @@
}
-unsigned int
-BaseCache::drain(DrainManager *dm)
-{
- int count = memSidePort->drain(dm) + cpuSidePort->drain(dm) +
- mshrQueue.drain(dm) + writeBuffer.drain(dm);
-
- // Set status
- if (count != 0) {
- setDrainState(DrainState::Draining);
- DPRINTF(Drain, "Cache not drained\n");
- return count;
- }
-
- setDrainState(DrainState::Drained);
- return 0;
-}
-
BaseCache *
BaseCacheParams::create()
{
diff -r 0ca18446a5bb -r b99a6662d7c2 src/mem/cache/base.hh
--- a/src/mem/cache/base.hh Tue Jul 07 09:51:04 2015 +0100
+++ b/src/mem/cache/base.hh Tue Jul 07 09:51:05 2015 +0100
@@ -593,8 +593,6 @@
// interesting again.
}
- virtual unsigned int drain(DrainManager *dm);
-
virtual bool inCache(Addr addr, bool is_secure) const = 0;
virtual bool inMissQueue(Addr addr, bool is_secure) const = 0;
diff -r 0ca18446a5bb -r b99a6662d7c2 src/mem/coherent_xbar.cc
--- a/src/mem/coherent_xbar.cc Tue Jul 07 09:51:04 2015 +0100
+++ b/src/mem/coherent_xbar.cc Tue Jul 07 09:51:05 2015 +0100
@@ -834,20 +834,6 @@
}
}
-unsigned int
-CoherentXBar::drain(DrainManager *dm)
-{
- // sum up the individual layers
- unsigned int total = 0;
- for (auto l: reqLayers)
- total += l->drain(dm);
- for (auto l: respLayers)
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